Sherry Kirkman Lee

US Patent:

6795952, Sep 21, 2004

Filed:

Nov 20, 2002

Appl. No.:

10/130448

Inventors:

Brian E. Stine - Santa Clara CA
David M. Stashower - Los Gatos CA
Sherry F. Lee - San Jose CA
Kurt H. Weiner - San Jose CA

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 945

US Classification:

716 5, 716 4

Abstract:

A system and method for predicting yield of integrated circuits includes a characterization vehicle ( ) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle ( ) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model ( ). The yield model ( ) embodies a layout as defined by the characterization vehicle ( ) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine ( ) extracts predetermined layout attributes ( ) from a proposed product layout ( ). Operating on the yield model, the extraction engine ( ) produces yield predictions ( ) as a function of layout attributes ( ) and broken down by layers or steps in the fabrication process ( ).

US Patent:

6901564, May 31, 2005

Filed:

Jul 18, 2002

Appl. No.:

10/200045

Inventors:

Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F017/50
G06F019/00

US Classification:

716 4, 700121

Abstract:

A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

US Patent:

7174521, Feb 6, 2007

Filed:

Mar 10, 2005

Appl. No.:

11/078630

Inventors:

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 703 2

Abstract:

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

US Patent:

7356800, Apr 8, 2008

Filed:

Aug 10, 2006

Appl. No.:

11/503323

Inventors:

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 21, 716 4, 716 19

Abstract:

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

US Patent:

7373625, May 13, 2008

Filed:

Aug 10, 2006

Appl. No.:

11/503433

Inventors:

Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 19, 716 21

Abstract:

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

US Patent:

7487474, Feb 3, 2009

Filed:

Nov 17, 2003

Appl. No.:

10/541076

Inventors:

Dennis Ciplickas - San Jose CA, US
Joe Davis - Unterschleissheim, DE
Christopher Hess - San Ramon CA, US
Sherry Lee - San Jose CA, US
Enrico Malavasi - Mountain View CA, US
Ratibor Radojcic - San Diego CA, US
Brian Stine - Los Altos Hills CA, US
Rakesh Vallishayee - San Jose CA, US
Stefano Zanella - San Jose CA, US
Nicola Dragone - Vobarno, IT
Carlo Guardiani - Verona, IT
Michel Quarantelli - Noceto, IT
Stefano Tonello - Breganze, IT
Joshi Aniruddha - Irvine CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 4, 716 5, 716 19, 716 20, 716 21

Abstract:

An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

US Patent:

7527987, May 5, 2009

Filed:

Dec 11, 2003

Appl. No.:

10/538538

Inventors:

Dennis Ciplickas - San Jose CA, US
Christopher Hess - San Carlos CA, US
Sherry Lee - San Jose CA, US
Larg Weiland - Livermore CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

H01L 21/66
G01R 31/26

US Classification:

438 14, 257 48, 257E21525

Abstract:

Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize defects on the test chip.

US Patent:

7673262, Mar 2, 2010

Filed:

May 13, 2008

Appl. No.:

12/119862

Inventors:

Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US

Assignee:

PDF Solutions, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 21

Abstract:

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.