Shih Yin Chang

US Patent:

20210098565, Apr 1, 2021

Filed:

Sep 26, 2019

Appl. No.:

16/584463

Inventors:

- Dallas TX, US
David Matthew CURRAN - Plano TX, US
Stephen Arlon MEISNER - Allen TX, US
Bhaskar SRINIVASAN - Allen TX, US
Guruvayurappan S. MATHUR - Plano TX, US
Scott William JESSEN - Allen TX, US
Shih Chang CHANG - Allen TX, US
Russell Duane FIELDS - Richardson TX, US
Thomas Terrance LYNCH - Allen TX, US

International Classification:

H01L 49/02

Abstract:

In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

US Patent:

20190198603, Jun 27, 2019

Filed:

Dec 27, 2017

Appl. No.:

15/855635

Inventors:

- Dallas TX, US
DHISHAN KANDE - DALLAS TX, US
QI-ZHONG HONG - RICHARDSON TX, US
SHIH CHANG CHANG - ALLEN TX, US

International Classification:

H01L 49/02
H01L 21/3213

Abstract:

A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.

US Patent:

20190157379, May 23, 2019

Filed:

Jan 4, 2019

Appl. No.:

16/240194

Inventors:

- Dallas TX, US
Guru Mathur - Plano TX, US
Stephen Arlon Meisner - Allen TX, US
Shih Chang Chang - Allen TX, US
Corinne Ann Gagnet - Dallas TX, US

International Classification:

H01L 49/02
H01L 21/768
H01L 21/02
H01L 27/108
H01L 29/16
H01L 27/06
H01L 29/66

Abstract:

An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.