Shih H Wang

US Patent:

7532119, May 12, 2009

Filed:

Nov 8, 2005

Appl. No.:

11/269237

Inventors:

Alexandre M. Bratkovski - Mountain View CA, US
Zhiyong Li - Palo Alto CA, US
Geoffrey Lyon - Menlo Park CA, US
Philip Kuekes - Menlo Park CA, US
Shih Yuang Wang - Palo Alto CA, US
R. Stanley Williams - Portola Valley CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G08B 13/14

US Classification:

3405721, 34053922

Abstract:

A multi-tiered network for gathering detected condition information includes a first tier having first tier nodes and a second tier having a second tier node. The second tier node is operable to receive detected condition information from at least one of the first tier nodes in a substantially autonomous manner. In addition, the second tier node is operable to at least one of store, process, and transmit the detected condition information. The network also includes a third tier having a third tier node configured to receive the detected condition information and to at least one of store and process the detected condition information.

US Patent:

7608530, Oct 27, 2009

Filed:

Mar 1, 2007

Appl. No.:

11/681080

Inventors:

Nobuhiko Kobayashi - Sunnyvale CA, US
Shih Yuan Wang - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438489, 257 51, 257 64, 257E29003, 977790, 977825

Abstract:

A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.

US Patent:

7875884, Jan 25, 2011

Filed:

Sep 8, 2009

Appl. No.:

12/555186

Inventors:

Nobuhiko Kobayashi - Sunnyvale CA, US
Shih Yuan Wang - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 31/036

US Classification:

257 51, 257 64, 257E29003, 438489, 977790, 977825

Abstract:

A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.

US Patent:

8183566, May 22, 2012

Filed:

Mar 1, 2007

Appl. No.:

11/681068

Inventors:

Nobuhiko Kobayashi - Sunnyvale CA, US
Shih Yuan Wang - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 29/06

US Classification:

257 51, 257 53, 257 64, 257 65, 257 81, 257E33076, 257E2109

Abstract:

A hetero-crystalline semiconductor device and a method of making the same include a non-single crystalline semiconductor layer and a nanostructure layer that comprises a single crystalline semiconductor nanostructure integral to a crystallite of the non-single crystalline semiconductor layer.

US Patent:

8283649, Oct 9, 2012

Filed:

Jul 28, 2009

Appl. No.:

12/510753

Inventors:

Alexandre M. Bratkovski - Mountain View CA, US
Shih Yuan Wang - Palo Alto CA, US
Jianhua Yang - Palo Alto CA, US
Michael Stuke - Palo Alto CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 29/04

US Classification:

257 3, 257E45003, 438381

Abstract:

A memristor includes a substrate having a plurality of protrusions, wherein each of the plurality of protrusions extends in a first direction, a first electrode provided over at least one of the plurality of protrusions, wherein the first electrode conforms to the shape of the at least one protrusion such that the first electrode has a crest, a switching material positioned upon the first electrode; and a second electrode positioned upon the switching material such that a portion of the second electrode is substantially in line with the crest of the first electrode along the first direction, wherein an active region in the switching material is operable to be formed between the crest of the first electrode and the portion of the second electrode that is substantially in line with the crest of the first electrode.

US Patent:

20060257067, Nov 16, 2006

Filed:

May 10, 2005

Appl. No.:

11/125135

Inventors:

Alexandre Bratkovski - Mountain View CA, US
Shih Wang - Palo Alto CA, US

International Classification:

G02B 6/00

US Classification:

385012000

Abstract:

A photonic crystal system and a method for controlling the direction of radiation propagation are disclosed. The photonic crystal system includes a photonic crystal and a deformation source positioned to deform the photonic crystal. The photonic crystal system optionally includes a radiation source that emits radiation at a frequency within a frequency range over which the photonic crystal exhibits a negative index of refraction.

US Patent:

51482673, Sep 15, 1992

Filed:

May 31, 1991

Appl. No.:

7/708950

Inventors:

Michael R. Ty Tan - Mountain View CA
Shih Y. Wang - Palo Alto CA
John L. Moll - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 29163
H01L 29203
H01L 2936
H01L 2986

US Classification:

357 16

Abstract:

A double heterostructure step recovery diode having a very fast step transition time and a high output voltage. A highly doped, wide bandgap p-type region; a narrow bandgap intrinsic region; and a highly doped, wide bandgap n-type region define a PIN diode structure. The intrinsic region forms heterojunctions with the p and n regions. Highly doped, narrow bandgap p and n contact regions adjoin the wide bandgap p and n regions, respectively and form heterojunctions therewith. Very thin, highly doped, narrow bandgap p and n regions are located between the intrinsic region and the wide bandgap p and n regions, respectively. Optional graded bandgap p-type and n-type regions are located between the wide and narrow bandgap p and n regions. In one embodiment the diode is embedded in an undoped wide bandgap material. In an alternate version, the intrinsic region is replaced with a lightly-doped p-type charge storage region to reduce the slow tail portion of the step recovery.