Shivakumar S Chonnad

US Patent:

6601024, Jul 29, 2003

Filed:

Nov 12, 1998

Appl. No.:

09/191153

Inventors:

Shivakumar Shankar Chonnad - Sunnyvale CA
Thomas Warren Savage - San Jose CA
Manickam E. Kandaswamy - Sunnyvale CA
Maulin Bhatt - San Jose CA
Christopher A. Kopetzky - Mountain View CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

703 14, 716 3

Abstract:

An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages. In addition, each module described using the first RTL description may be functionally compared with each module described using second RTL description.

US Patent:

20220269846, Aug 25, 2022

Filed:

Feb 24, 2022

Appl. No.:

17/680226

Inventors:

- Mountain View CA, US
Shivakumar Shankar CHONNAD - San Jose CA, US

International Classification:

G06F 30/3323
G06F 11/22

Abstract:

A method for determining fault types in a circuit design includes obtaining circuit elements, a first observation point of a first circuit element, and a first diagnostic point of a first safety circuit device. The method further includes determining a first cone of influence including a first subset of the circuit elements based on the first observation point. The first subset of the circuit elements includes the first circuit element. Further, the method includes determining a first safety cone including a second subset of the circuit elements based on the first diagnostic point. The first safety cone includes the first safety circuit device. The method further includes determining a fault type associated with the circuit elements based on an intersection between the first cone of influence and the first safety cone.