Shunsaku Tokito

US Patent:

7423900, Sep 9, 2008

Filed:

Nov 15, 2006

Appl. No.:

11/559982

Inventors:

Shunsaku Tokito - Austin TX, US

Assignee:

Sony Computer Entertainment Inc. - Tokyo

International Classification:

G11C 11/00

US Classification:

365154, 365203, 365189011

Abstract:

Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

US Patent:

7676683, Mar 9, 2010

Filed:

Aug 24, 2006

Appl. No.:

11/509493

Inventors:

Atsushi Tsuji - Kanagawa, JP
Chiaki Takano - Austin TX, US
Masaaki Nozaki - Kanagawa, JP
Shunsaku Tokito - Austin TX, US
Hiroaki Terakawa - Austin TX, US

Assignee:

Sony Computer Entertainment Inc. - Tokyo

International Classification:

G06F 1/00
G06F 9/00
G06F 13/00
G06F 12/00

US Classification:

713323, 713 1, 713300, 710104, 710242

Abstract:

Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.

US Patent:

7684231, Mar 23, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609631

Inventors:

Atsushi Hayashi - Kanagawa, JP
Shunsaku Tokito - Austin TX, US
Hiroshi Yoshihara - Round Rock TX, US
Yuuki Fujiyama - Tokyo, JP

Assignee:

Sony Computer Entertainment Inc. - Tokyo

International Classification:

G11C 11/00

US Classification:

365154, 36518907, 365190, 365227

Abstract:

Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

US Patent:

20070047349, Mar 1, 2007

Filed:

Sep 1, 2005

Appl. No.:

11/218009

Inventors:

Shunsaku Tokito - Austin TX, US

International Classification:

G11C 7/00

US Classification:

365203000

Abstract:

Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.