Shuo Zhang

US Patent:

7380231, May 27, 2008

Filed:

Jun 6, 2005

Appl. No.:

11/146485

Inventors:

Shuo Zhang - San Jose CA, US
Fangyi Luo - Santa Cruz CA, US

Assignee:

Nannor Technologies - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 12, 716 2, 716 11

Abstract:

The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS) and a top-down shape (TDS). The BUS and TDS are merged to form a final geometrical Middle Shape (MS). Each point in the MS has a position is averaged from the positions of the two correlated points in the BUS and TDS. Unnecessary short jogs are removed from the MS of each wire. A final layout is generated by combining all of the final geometric shapes of each wire segments. As such, the wire-to-wire spacing is increased to more than the minimum spacing requirement without causing any design rule violations.

US Patent:

7526746, Apr 28, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/450142

Inventors:

Shuo Zhang - Mountain View CA, US
Yongbo Jia - Fremont CA, US

Assignee:

Nannor Technologies - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 2

Abstract:

Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable. Geotopological layout optimization according to the present invention can be performed on an entire layout, or it can be performed incrementally on one or more sub-layouts of a design.

US Patent:

20060064653, Mar 23, 2006

Filed:

Sep 21, 2004

Appl. No.:

10/946686

Inventors:

Shuo Zhang - Sunnyvale CA, US
Yongbo Jia - Fremont CA, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716002000, 716010000, 716013000

Abstract:

The present invention provides a new way of improving yield in the physical design stage after detail routing, thereby optimizing integrated circuit (IC) layout designs for manufacturing. Embodied in an automatic layout yield improvement tool, the present invention replaces vias with redundant vias having redundant cut shapes or larger metal overlapping based on a novel geotopological approach to routed layout optimization. The geotopological approach enables the most favorable redundant via candidate to be selected for each modifiable regular via. The tool first checks all potential redundant vias in the order of yield favorableness. The modifiable regular via is then replaced by an ideal redundant via that does not introduce any design rule violations in the geotopological layout. Overcoming the fundamental limitation of geometrical-based solutions and taking advantage of the modification flexibility of the geotopological approach, this invention achieves highly desirable redundant via usage rate and substantial yield improvement.

US Patent:

20060064654, Mar 23, 2006

Filed:

Sep 21, 2004

Appl. No.:

10/946918

Inventors:

Shuo Zhang - Sunnyvale CA, US
Yongbo Jia - Fremont CA, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716002000, 716012000, 716009000

Abstract:

The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.

US Patent:

20140228384, Aug 14, 2014

Filed:

May 29, 2013

Appl. No.:

13/904922

Inventors:

- South San Francisco CA, US
Donald Kirkpatrick - San Mateo CA, US
Tracy Kleinheinz - Daly City CA, US
John Moffat - San Francisco CA, US
Zejuan Sheng - San Mateo CA, US
Shuo Zhang - Belmont CA, US
Haitao Zhu - Palo Alto CA, US

International Classification:

G01N 33/573

US Classification:

514275, 435 15, 435 74

Abstract:

Biomarkers for screening subjects for Parkinson's disease and providing companion diagnostic tools for therapies using LRRK2 modulators, and assays for screening compounds and compositions for modulation of LRRK2 activity.