Siegfried L Maurer from 26 Blueberry Ln, Stormville, NY 12582, age 70, Phone: (845)2211963

Resumes

Staff Engineer

view source

Location:

26 Blueberry Ln, Stormville, NY 12582

Industry:

Information Technology And Services

Work:

Ibm
Staff Engineer

Skills:

Project Management

Us Patents

Control Of Buried Oxide In Simox
view source
US Patent:

6784072, Aug 31, 2004
Filed:

Jul 22, 2002
Appl. No.:

10/200822
Inventors:

Stephen Richard Fox - Hopewell Junction NY
Neena Garg - Fishkill NY
Kenneth John Giewont - Hopewell Junction NY
Junedong Lee - Hopewell Junction NY
Siegfried Lutz Maurer - Stormville NY
Dan Moy - Bethel CT
Maurice Heathcote Norcott - San Jose CA
Devendra Kumar Sadana - Pleasantville NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2176
US Classification:

438404, 438407, 438528
Abstract:

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V.

Control Of Buried Oxide In Simox
view source
US Patent:

7492008, Feb 17, 2009
Filed:

Jul 22, 2004
Appl. No.:

10/896812
Inventors:

Stephen Richard Fox - Hopewell Junction NY, US
Neena Garg - Fishkill NY, US
Kenneth John Giewont - Hopewell Junction NY, US
Junedong Lee - Hopewell Junction NY, US
Siegfried Lutz Maurer - Stormville NY, US
Dan Moy - Bethel CT, US
Maurice Heathcote Norcott - San Jose CA, US
Devendra Kumar Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/336
US Classification:

257347, 257353, 257E27112
Abstract:

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V.

Thin Buried Oxides By Low-Dose Oxygen Implantation Into Modified Silicon
view source
US Patent:

7718231, May 18, 2010
Filed:

Sep 30, 2003
Appl. No.:

10/674647
Inventors:

Kwang Su Choe - Sungnam-Shi, KR
Keith E. Fogel - Mohegan Lake NY, US
Siegfried L. Maurer - Stormville NY, US
Ryan M. Mitchell - Clintondale NY, US
Devendra K. Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

C23C 14/10
C23C 14/48
C23C 14/58
H01L 21/762
US Classification:

427526, 427527, 438766, 438769, 438771, 438762, 438378, 438440, 438441
Abstract:

A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

N-Type Carrier Enhancement In Semiconductors
view source
US Patent:

8178430, May 15, 2012
Filed:

Apr 8, 2009
Appl. No.:

12/420258
Inventors:

Jee Hwan Kim - White Plains NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Siegfried Maurer - Stormville NY, US
Devendra K. Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/265
H01L 21/425
US Classification:

438527, 438919, 257E21335
Abstract:

A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached.

Method To Enable The Process And Enlarge The Process Window For Silicide, Germanide Or Germanosilicide Formation In Structures With Extremely Small Dimensions
view source
US Patent:

8247319, Aug 21, 2012
Filed:

Feb 7, 2011
Appl. No.:

13/022474
Inventors:

Benjamin Luke Fletcher - Elmsford NY, US
Christian Lavoie - Pleasantville NY, US
Siegfried Lutz Maurer - Stormville NY, US
Zhen Zhang - Ossining NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/28
H01L 21/44
US Classification:

438581, 438583, 438664, 438682, 257E21164, 257E21165, 977890, 977900
Abstract:

Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.

N-Type Carrier Enhancement In Semiconductors
view source
US Patent:

8343863, Jan 1, 2013
Filed:

Jan 25, 2012
Appl. No.:

13/357656
Inventors:

Jee Hwan Kim - White Plains NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Siegfried Maurer - Stormville NY, US
Devendra K. Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/265
H01L 21/336
US Classification:

438529, 257E21336, 25049221, 427523
Abstract:

A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached.

Cmos Transistors With Stressed High Mobility Channels
view source
US Patent:

8354694, Jan 15, 2013
Filed:

Aug 13, 2010
Appl. No.:

12/855738
Inventors:

Stephen W. Bedell - Wappingers Falls NY, US
Jee H. Kim - Los Angeles CA, US
Siegfried L. Maurer - Stormville NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 29/66
US Classification:

257192, 257342
Abstract:

A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

N-Type Carrier Enhancement In Semiconductors
view source
US Patent:

8476152, Jul 2, 2013
Filed:

Mar 31, 2012
Appl. No.:

13/436850
Inventors:

Jee Hwan Kim - White Plains NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Siegfried Maurer - Stormville NY, US
Devendra K. Sadana - Pleasantville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/265
US Classification:

438514, 438919, 117936, 257E21335, 257E21336
Abstract:

A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.