Siu F Chan

US Patent:

7170784, Jan 30, 2007

Filed:

Apr 1, 2005

Appl. No.:

11/097502

Inventors:

Siu Lung Chan - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34
G11C 16/06

US Classification:

36518512, 36518503, 36518521

Abstract:

Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.

US Patent:

7173854, Feb 6, 2007

Filed:

Apr 1, 2005

Appl. No.:

11/097038

Inventors:

Siu Lung Chan - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34
G11C 16/04
G11C 16/24
G11C 16/26

US Classification:

36518512, 3651852, 3652385, 36518909, 36518503

Abstract:

Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.

US Patent:

7206235, Apr 17, 2007

Filed:

Oct 14, 2005

Appl. No.:

11/251458

Inventors:

Jeffrey W. Lutze - San Jose CA, US
Yan Li - Milpitas CA, US
Siu L. Chan - San Jose CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

G11C 7/00

US Classification:

365195, 36518502, 36518517, 36518518, 36518524

Abstract:

The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

US Patent:

7224614, May 29, 2007

Filed:

Dec 29, 2005

Appl. No.:

11/323596

Inventors:

Siu Lung Chan - San Jose CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

G11C 16/06

US Classification:

36518522, 36518518, 36518519, 3651852, 36518524, 36518503

Abstract:

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

US Patent:

7251160, Jul 31, 2007

Filed:

Mar 16, 2005

Appl. No.:

11/083514

Inventors:

Yan Li - Milpitas CA, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

G11C 11/34

US Classification:

36518503, 36518522, 36518524

Abstract:

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

US Patent:

7286406, Oct 23, 2007

Filed:

Oct 14, 2005

Appl. No.:

11/250735

Inventors:

Jeffrey W. Lutze - San Jose CA, US
Yan Li - Milpitas CA, US
Siu L. Chan - San Jose CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

G11C 16/04

US Classification:

36518518, 36518517, 36518523

Abstract:

The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

US Patent:

7310255, Dec 18, 2007

Filed:

Dec 29, 2005

Appl. No.:

11/323577

Inventors:

Siu Lung Chan - San Jose CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34

US Classification:

365 22, 36518503, 36518524

Abstract:

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

US Patent:

7324393, Jan 29, 2008

Filed:

Dec 28, 2005

Appl. No.:

11/321681

Inventors:

Siu Lung Chan - San Jose CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

G11C 7/00

US Classification:

365205, 365207, 36518901, 36518907, 36518521

Abstract:

One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.