Siu Y Cheng

US Patent:

8278139, Oct 2, 2012

Filed:

Sep 25, 2009

Appl. No.:

12/566948

Inventors:

Siu F. Cheng - San Jose CA, US
Deenesh Padhi - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/02

US Classification:

438102, 438104, 438382, 438384, 438628, 257 4, 257E45002, 257E21003, 257E21004, 257E21005

Abstract:

A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.

US Patent:

20090269512, Oct 29, 2009

Filed:

Apr 28, 2008

Appl. No.:

12/110879

Inventors:

Jianhua Zhou - San Jose CA, US
Deenesh Padhi - Sunnyvale CA, US
Karthik Janakiraman - San Jose CA, US
Hang Yu - Santa Clara CA, US
Siu F. Cheng - San Jose CA, US
Yoganand Saripalli - Sunnyvale CA, US
Tersem Summan - San Jose CA, US

International Classification:

C23C 16/44

US Classification:

427569, 118723 I

Abstract:

A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode.

US Patent:

20110159211, Jun 30, 2011

Filed:

Dec 21, 2010

Appl. No.:

12/974365

Inventors:

Dale R. Du Bois - Los Gatos CA, US
Mohamad A. Ayoub - Las Gatos CA, US
Robert Kim - Mountain View CA, US
Amit Bansal - Santa Clara CA, US
Mark Fodor - Los Gatos CA, US
Binh Nguyen - San Jose CA, US
Siu F. Cheng - Los Angeles CA, US
Hang Yu - Woodland CA, US
Chiu Chan - Foster City CA, US
Ganesh Balasubramanian - Sunnyvale CA, US
Deenesh Padhi - Sunnyvale CA, US
Juan Carlos Rocha - San Carlos CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

C23C 16/00
B05C 11/00

US Classification:

427569, 118 71

Abstract:

Embodiments of the invention contemplate a shadow ring that provides increased or decreased and more uniform deposition on the edge of a wafer. By removing material from the top and/or bottom surfaces of the shadow ring, increased edge deposition and bevel coverage can be realized. In one embodiment, the material on the bottom surface is reduced by providing a recessed slot on the bottom surface. By increasing the amount of material of the shadow ring, the edge deposition and bevel coverage is reduced. Another approach to adjusting the deposition at the edge of the wafer includes increasing or decreasing the inner diameter of the shadow ring. The material forming the shadow ring may also be varied to change the amount of deposition at the edge of the wafer.

US Patent:

20110244142, Oct 6, 2011

Filed:

Mar 30, 2010

Appl. No.:

12/750378

Inventors:

SIU F. CHENG - San Jose CA, US
Jacob Janzen - Lorsch, DE
Deenesh Padhi - Sunnyvale CA, US
Bok Hoen Kim - San Jose CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

C23C 16/513

US Classification:

427569

Abstract:

Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate.

US Patent:

20190153592, May 23, 2019

Filed:

Jan 28, 2019

Appl. No.:

16/259011

Inventors:

- Santa Clara CA, US
Mohamad A. AYOUB - Los Gatos CA, US
Robert KIM - San Francisco CA, US
Amit Kumar BANSAL - Milpitas CA, US
Mark FODOR - Los Gatos CA, US
Binh NGUYEN - San Jose CA, US
Siu F. CHENG - Culver City CA, US
Hang YU - Woodland CA, US
Chiu CHAN - Foster City CA, US
Ganesh BALASUBRAMANIAN - Fremont CA, US
Deenesh PADHI - Sunnyvale CA, US
Juan Carlos ROCHA - San Carlos CA, US

International Classification:

C23C 16/04
C23C 16/458
C23C 16/455
C23C 16/44
H01J 37/32
C23C 14/04
H01L 21/687
C30B 25/12
H01J 37/34

Abstract:

Embodiments of the invention contemplate a shadow ring that provides increased or decreased and more uniform deposition on the edge of a wafer. By removing material from the top and/or bottom surfaces of the shadow ring, increased edge deposition and bevel coverage can be realized. In one embodiment, the material on the bottom surface is reduced by providing a recessed slot on the bottom surface. By increasing the amount of material of the shadow ring, the edge deposition and bevel coverage is reduced. Another approach to adjusting the deposition at the edge of the wafer includes increasing or decreasing the inner diameter of the shadow ring. The material forming the shadow ring may also be varied to change the amount of deposition at the edge of the wafer.