Sivakumar Radhakrishnan

US Patent:

6496516, Dec 17, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206697

Inventors:

Stephen Dabecki - Maple Ridge, CA
Sivakumar Radhakrishnan - Hillsboro OR

Assignee:

PMC-Sierra, Ltd.

International Classification:

H04L 1243

US Classification:

370460, 370406, 370413, 370415, 370417

Abstract:

A ring interface is coupled to a current node in a ring network having a plurality of nodes and corresponding ring interface for each of said nodes. The ring interface includes a ring input port operative to conduct upstream message packets from a previous node to the ring interface, a ring output port operative to conduct message packets to a next node of the ring network, and a bypass queue operative to buffer message packets. A receive queue buffers message packets before passing them on to the current node. An address filter is coupled to the ring input port to receive the upstream message packets, read their destination addresses and pass them to the bypass queue if the addresses correspond to another node and pass them to the receive queue if their addresses are that of the current node. A transmit queue buffers message packets from the current node and a bypass-transmit queue arbiter is coupled to outputs of the bypass queue and the transmit queue and is operative to select message packets from one of the bypass queue and the transmit queue in accordance with predetermined selection criterion and transmits the selected message packets to the ring output port.

US Patent:

7353301, Apr 1, 2008

Filed:

Oct 29, 2004

Appl. No.:

10/977235

Inventors:

Sivakumar Radhakrishnan - Portland OR, US
Siva Balasubramanian - Chandler AZ, US
William T. Futral - Portland OR, US
Sujoy Sen - Portland OR, US
Gregory D. Cummings - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US
David C. Lee - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06G 3/00

US Classification:

710 33, 710 30

Abstract:

Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

US Patent:

7386640, Jun 10, 2008

Filed:

Dec 28, 2004

Appl. No.:

11/025381

Inventors:

David C. Lee - Beaverton OR, US
Steve Kulick - Portland OR, US
Sivakumar Radhakrishnan - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00

US Classification:

710 19, 710 48, 710302, 710260

Abstract:

In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

US Patent:

7400945, Jul 15, 2008

Filed:

Mar 23, 2005

Appl. No.:

11/088445

Inventors:

Sivakumar Radhakrishnan - Portland OR, US
Michael Wiznerowicz - Beaverton OR, US
Jed D. Griffin - Forest Grove OR, US
Kapilan Maheswaran - Beaverton OR, US
Scott Rushford - Hillsboro OR, US
David J. Hotz - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00
B29C 45/00
G05B 9/02

US Classification:

700299, 700108, 700205, 702130, 702131, 702132, 713501

Abstract:

Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on the semiconductor device, comparing the detected temperature to a threshold, and generating a high interrupt if the temperature is above the threshold and a low interrupt if the temperature is below the threshold.

US Patent:

7500029, Mar 3, 2009

Filed:

Oct 29, 2004

Appl. No.:

10/977230

Inventors:

Sivakumar Radhakrishnan - Portland OR, US
Siva Balasubramanian - Chandler AZ, US
Sin S. Tan - Portland OR, US
Suneeta Sah - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00

US Classification:

710 33, 710 30

Abstract:

Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

US Patent:

8006017, Aug 23, 2011

Filed:

Dec 21, 2004

Appl. No.:

11/020500

Inventors:

William T. Futral - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US
Sujoy Sen - Portland OR, US
Gregory D. Cummings - Portland OR, US
Sivakumar Radhakrishnan - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14
G06F 13/38

US Classification:

710244, 710305

Abstract:

A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

US Patent:

8122265, Feb 21, 2012

Filed:

Dec 29, 2006

Appl. No.:

11/648253

Inventors:

Sivakumar Radhakrishnan - Portland OR, US
Suneeta Sah - Portland OR, US
William H. Nale - Livermore CA, US
Rami Naqib - Portland OR, US
Howard S. David - Portland OR, US
Rajat Agarwal - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713300, 713320, 711100, 711154

Abstract:

In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

US Patent:

8205026, Jun 19, 2012

Filed:

Aug 23, 2011

Appl. No.:

13/216230

Inventors:

William T. Futral - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US
Sujoy Sen - Portland OR, US
Gregory D. Cummings - Portland OR, US
Sivakumar Radhakrishnan - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14
G06F 13/38

US Classification:

710244, 710305

Abstract:

A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.