Sorin F Iacobovici from 3181 Acorn Way, San Jose, CA 95117, age 80, Phone: (408)2556102

Resumes

Distinguished Engineer

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Location:

San Francisco, CA

Industry:

Computer Hardware

Work:

Sun Microsystems
Distinguished Engineer

Us Patents

Method And Apparatus For Handling Data Errors In A Computer System
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US Patent:

6453427, Sep 17, 2002
Filed:

Dec 31, 1998
Appl. No.:

09/224380
Inventors:

Nhon T. Quach - San Jose CA
John W. C. Fu - Saratoga CA
James O. Hays - San Jose CA
Valentin Anders - San Jose CA
Sorin Iacobovici - San Jose CA
Alberto J. Munoz - Los Altos CA
Dean A. Mulla - Fort Collins CO
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1100
US Classification:

714 6, 711122
Abstract:

An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Microprocessor Speed Control Mechanism Using Power Dissipation Estimation Based On The Instruction Data Path
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US Patent:

6704876, Mar 9, 2004
Filed:

Sep 26, 2000
Appl. No.:

09/669346
Inventors:

Sorin Iacobovici - San Jose CA
Ronald Melanson - Woodside CA
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 126
US Classification:

713300, 713320, 713322
Abstract:

A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

Forming Linked Lists Using Content Addressable Memory
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US Patent:

6820086, Nov 16, 2004
Filed:

Jun 18, 1999
Appl. No.:

09/336046
Inventors:

Sorin Iacobovici - San Jose CA
William R. Bryg - Saratoga CA
Joseph H. Hassoun - Pleasanton CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 700
US Classification:

707100, 711108, 711118, 707 1
Abstract:

A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.

Register Window Spill Technique For Retirement Window Having Entry Size Less Than Amount Of Spill Instructions
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US Patent:

7024541, Apr 4, 2006
Filed:

Jun 7, 2002
Appl. No.:

10/165268
Inventors:

Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 15/00
US Classification:

712218, 712228, 712243
Abstract:

A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Register Window Fill Technique For Retirement Window Having Entry Size Less Than Amount Of Fill Instructions
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US Patent:

7035999, Apr 25, 2006
Filed:

Jun 7, 2002
Appl. No.:

10/165256
Inventors:

Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/22
US Classification:

712218, 712228, 712243
Abstract:

A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Method And Apparatus For Protecting A State Associated With A Memory Structure
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US Patent:

7043609, May 9, 2006
Filed:

Feb 3, 2003
Appl. No.:

10/357643
Inventors:

Victor Melamed - Sunnyvale CA, US
Sorin Iacobovici - San Jose CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 12/08
US Classification:

711144, 711145, 711156, 714 6
Abstract:

A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state information is identified from the state information. Next, a copy of the crucial state information is generated. Then, the state information and the copy of the crucial state information are protected. Next, a worst case state associated with non-crucial information is defined. In response to detecting an error associated with the non-crucial information, the method includes defaulting to the worst case state. A computer readable media and a shared memory multiprocessor chip are also provided.

Method For Handling Condition Code Modifiers In An Out-Of-Order Multi-Issue Multi-Stranded Processor
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US Patent:

7065635, Jun 20, 2006
Filed:

Dec 17, 2003
Appl. No.:

10/738576
Inventors:

Rabin A. Sugumar - Sunnyvale CA, US
Sorin Iacobovici - San Jose CA, US
Chandra M. R. Thimmannagari - Fremont CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/38
US Classification:

712228, 712217
Abstract:

A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

Register Window Flattening Logic For Dependency Checking Among Instructions
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US Patent:

7080237, Jul 18, 2006
Filed:

May 24, 2002
Appl. No.:

10/155391
Inventors:

Chandra M. R. Thimmannagari - Fremont CA, US
Sorin Iacobovici - San Jose CA, US
Rabin A. Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/30
US Classification:

712220, 712216
Abstract:

A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.