Sridhar Kotha

US Patent:

6542150, Apr 1, 2003

Filed:

Jun 28, 1996

Appl. No.:

08/671873

Inventors:

Sridhar Kotha - Fremont CA
Vlad Bril - Campbell CA
Alexander J. Eglit - Half Moon Bay CA

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

G09G 500

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

7209133, Apr 24, 2007

Filed:

Feb 7, 2003

Appl. No.:

10/359734

Inventors:

Alexander J. Eglit - Half Moon Bay CA, US
Sridhar Kotha - Fremont CA, US
Vlad Bril - Campbell CA, US

Assignee:

NVIDIA International, Inc. - St. Michael

International Classification:

G09G 5/00
G09G 3/18

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

7623126, Nov 24, 2009

Filed:

Jun 17, 2003

Appl. No.:

10/463840

Inventors:

Alexander J. Eglit - Half Moon Bay CA, US
Sridhar Kotha - Fremont CA, US
Vlad Bril - Campbell CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/00
G09G 3/18

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

56821700, Oct 28, 1997

Filed:

Jul 31, 1995

Appl. No.:

8/509651

Inventors:

Sridhar Kotha - Fremont CA
Alexander Eglit - San Carlos CA
Robin Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 300
G09G 500

US Classification:

345 3

Abstract:

A method and apparatus for horizontally and vertically positioning a video graphics adapter (VGA) display image on the screen of a flat panel display (FPD) is provided with a first counter for setting a horizontal FPD disable period associated with the FPD. A second counter sets the horizontal FPD enable period of the FPD. This horizontal FPD enable period is greater than a composite horizontal pixel time of a VGA image to be displayed. A first circuit controls the start time of a subsequent horizontal FPD enable period. This start time is based on the horizontal FPD disable period. A second circuit controls the end time of the subsequent horizontal FPD enable period. This end time is based on the horizontal FPD enable period. The VGA display image is begun based on the start time of the subsequent horizontal FPD enable period to locate the VGA display image at a desired horizontal position of the FPD screen. The vertical positioning of the image is performed by similar counters and circuits.

US Patent:

58414185, Nov 24, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/483584

Inventors:

Vald Bril - Campbell CA
Rakesh Bindlish - San Jose CA
Ken Fuiks - Fremont CA
Robin Sungsoo Han - Saratoga CA
Sridhar Kotha - Fremont CA
Alexander Julian Eglit - San Carlos CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 500

US Classification:

345 3

Abstract:

A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e. g. , CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e. g. , CRT or LCD) of the video data.

US Patent:

62190407, Apr 17, 2001

Filed:

Oct 5, 1999

Appl. No.:

9/412320

Inventors:

Sridhar Kotha - Fremont CA

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

G09G 500

US Classification:

345211

Abstract:

The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e. g. , laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals.

US Patent:

60670711, May 23, 2000

Filed:

Jun 27, 1996

Appl. No.:

8/673793

Inventors:

Sridhar Kotha - Fremont CA
Vlad Bril - Campbell CA
Alexander J. Eglit - Half Moon Bay CA
Robin Sungsoo Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 336

US Classification:

345132

Abstract:

A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA. TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.

US Patent:

55216145, May 28, 1996

Filed:

Apr 29, 1994

Appl. No.:

8/235827

Inventors:

Sridhar Kotha - Fremont CA
Alexander Eglit - San Carlos CA
Robin Han - Saratoga CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 526
G09G 536

US Classification:

345128

Abstract:

A method and apparatus for expanding a video graphics adapter (VGA) text character to fully fill the screen of a flat panel display. The present invention stores binary information representing a horizontal row of character text. A prescribed bit in the binary information may be set to determine whether to duplicate pixels associated with the binary information in either a horizontal or vertical direction. A circuit is provided to ensure that foreground and background characteristics of the graphics character text being expanded are consistent with the sent prescribed bit in the binary information.