Stacy Lea Freeman

US Patent:

6563223, May 13, 2003

Filed:

Dec 7, 2001

Appl. No.:

10/013090

Inventors:

Stacy L. Freeman - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2348

US Classification:

257778, 257696, 257701, 257712, 257726, 257727

Abstract:

Apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. In one embodiment, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins. In an alternate embodiment, an apparatus further includes a semiconductor component having a plurality of conductive bumps disposed thereon.

US Patent:

6562641, May 13, 2003

Filed:

Aug 22, 2000

Appl. No.:

09/644196

Inventors:

Stacy L. Freeman - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2166

US Classification:

438 18, 257678

Abstract:

Apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. In one embodiment, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins. In an alternate embodiment, an apparatus further includes a semiconductor component having a plurality of conductive bumps disposed thereon.