Stephanie A Butler

US Patent:

6787425, Sep 7, 2004

Filed:

Jun 16, 2003

Appl. No.:

10/462409

Inventors:

Antonio Luis Pacheco Rotondaro - Dallas TX
Trace Quentin Hurd - Plano TX
Stephanie Watts Butler - Richardson TX
Majid M. Mansoori - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438300, 438682

Abstract:

Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.

US Patent:

7704883, Apr 27, 2010

Filed:

Dec 22, 2006

Appl. No.:

11/615456

Inventors:

Stephanie W. Butler - Richardson TX, US
Yuanning Chen - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438689, 257E33074, 257E29106, 257E21012, 257E21013, 257E21028

Abstract:

A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

US Patent:

7752518, Jul 6, 2010

Filed:

Feb 13, 2008

Appl. No.:

12/030365

Inventors:

Cloves R. Cleavelin - Dallas TX, US
Andrew Marshall - Dallas TX, US
Stephanie W. Butler - Richardson TX, US
Howard L. Tigelaar - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714733, 714718, 714727, 365201

Abstract:

An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

US Patent:

7793186, Sep 7, 2010

Filed:

May 20, 2010

Appl. No.:

12/784078

Inventors:

Cloves R. Cleavelin - Dallas TX, US
Andrew Marshall - Dallas TX, US
Stephanie W. Butler - Richardson TX, US
Howard L. Tigelaar - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714733, 714718, 714727, 365201

Abstract:

An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

US Patent:

54023670, Mar 28, 1995

Filed:

Jul 19, 1993

Appl. No.:

8/093842

Inventors:

Michael F. Sullivan - Dallas TX
Judith S. Hirsch - Plano TX
Stephanie W. Butler - Plano TX
Nicholas J. Tovell - Plano TX
Jerry A. Stefani - Richardson TX
Purnendu K. Mozumder - Dallas TX
Ulrich H. Wild - Dallas TX
Chun-Jen J. Wang - Richardson TX
Robert A. Hartzell - Sacramento CA

Assignee:

Texas Instruments, Incorporated - Dallas TX

International Classification:

G05B 1304

US Classification:

364578

Abstract:

The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.

US Patent:

58647732, Jan 26, 1999

Filed:

Nov 1, 1996

Appl. No.:

8/743113

Inventors:

Gabriel G. Barna - Richardson TX
Stephanie W. Butler - Plano TX
Donald A. Sofge - Leesburg VA
David A. White - Cambridge MA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01B 700

US Classification:

702 85

Abstract:

A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state. A rule based logic system (26) is operable to receive and process the signals provided by the plurality of equipment sensors (14) and the output signals provided by the virtual sensors (24) to monitor processing equipment (12) or to detect and classify faults within the processing equipment (12).

US Patent:

53992296, Mar 21, 1995

Filed:

May 13, 1993

Appl. No.:

8/061983

Inventors:

Jerry A. Stefani - Richardson TX
Stephanie W. Butler - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306
B44C 122

US Classification:

156626

Abstract:

A system (60) and method for monitoring, evaluating and controlling the uniformity of a semiconductor wafer fabrication process is provided for use in manufacturing integrated circuits on semiconductor wafers (40). By using in situ ellipsometry (20) in conjunction with statistical modeling methods, the spatial etch rate pattern across a semiconductor wafer (40) may be inferred as a function of the process conditions. A predicted mean etch rate may be calculated for other locations (46 and 48) on the semiconductor wafer surface (42) by using the mean etch rate measured at the selected ellipsometer site (44) and individual spatial etch rate models developed for each site (44 and 48) based on statistically designed experiments. The predicted mean etch rate at the other sites (46 and 48) is also a function of the fabrication process conditions. The method for evaluating uniformity may be used with fabrication processes such as oxidation, doping, etching or any other process which may be measured in situ at a selected location (44) on a semiconductor wafer (40) during the fabrication process.

US Patent:

58385959, Nov 17, 1998

Filed:

Nov 25, 1996

Appl. No.:

8/755689

Inventors:

Michael Francis Sullivan - Dallas TX
Judith Susan Hirsch - Plano TX
Stephanie Watts Butler - Plano TX
Nicholas John Tovell - Plano TX
Jerry Alan Stefani - Richardson TX
Purnendu K. Mozumder - Dallas TX
Ulrich H. Wild - Dallas TX
Chun-Jen Jason Wang - Richardson TX
Robert A. Hartzell - Sacramento CA

Assignee:

Texas Instruments, Inc. - Dallas TX

International Classification:

G05B 1304

US Classification:

364578

Abstract:

The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.