Stephanie L Butler

US Patent:

6787425, Sep 7, 2004

Filed:

Jun 16, 2003

Appl. No.:

10/462409

Inventors:

Antonio Luis Pacheco Rotondaro - Dallas TX
Trace Quentin Hurd - Plano TX
Stephanie Watts Butler - Richardson TX
Majid M. Mansoori - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438300, 438682

Abstract:

Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.

US Patent:

6808997, Oct 26, 2004

Filed:

Mar 21, 2003

Appl. No.:

10/393749

Inventors:

Amitabh Jain - Allen TX
Stephanie W. Butler - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438305, 438390, 438395

Abstract:

Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

US Patent:

6812073, Nov 2, 2004

Filed:

Dec 10, 2002

Appl. No.:

10/316468

Inventors:

Haowen Bu - Plano TX
Amitabh Jain - Allen TX
Wayne A. Bather - Richardson TX
Stephanie Watts Butler - Richardson TX

Assignee:

Texas Instrument Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438151, 438231, 438287

Abstract:

A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

US Patent:

7345355, Mar 18, 2008

Filed:

Sep 15, 2004

Appl. No.:

10/942607

Inventors:

Amitabh Jain - Allen TX, US
Stephanie W. Butler - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/00
H01L 31/0288

US Classification:

257607, 257463, 257465, 257545, 257548, 438305, 438390, 438395, 438252

Abstract:

Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

US Patent:

7531398, May 12, 2009

Filed:

Oct 19, 2006

Appl. No.:

11/583280

Inventors:

Zhibo Zhang - Plano TX, US
Cloves Rinn Cleavelin - Dallas TX, US
Michael Francis Pas - Richardson TX, US
Stephanie Watts Butler - Richardson TX, US
Mike Watson Goodwin - Murphy TX, US
Satyavolu Srinivas Papa Rao - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438680, 438679, 438684, 257E2117, 257E21051, 257E21278, 257E21267, 257E21435

Abstract:

A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

US Patent:

7704883, Apr 27, 2010

Filed:

Dec 22, 2006

Appl. No.:

11/615456

Inventors:

Stephanie W. Butler - Richardson TX, US
Yuanning Chen - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438689, 257E33074, 257E29106, 257E21012, 257E21013, 257E21028

Abstract:

A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

US Patent:

7752518, Jul 6, 2010

Filed:

Feb 13, 2008

Appl. No.:

12/030365

Inventors:

Cloves R. Cleavelin - Dallas TX, US
Andrew Marshall - Dallas TX, US
Stephanie W. Butler - Richardson TX, US
Howard L. Tigelaar - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714733, 714718, 714727, 365201

Abstract:

An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

US Patent:

7793186, Sep 7, 2010

Filed:

May 20, 2010

Appl. No.:

12/784078

Inventors:

Cloves R. Cleavelin - Dallas TX, US
Andrew Marshall - Dallas TX, US
Stephanie W. Butler - Richardson TX, US
Howard L. Tigelaar - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714733, 714718, 714727, 365201

Abstract:

An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.