Stephen Harris Burger

US Patent:

6393544, May 21, 2002

Filed:

Oct 31, 1999

Appl. No.:

09/430793

Inventors:

William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
Gary N. Hammond - Fort Collins CO
James O. Hays - San Jose CA
Jerome C. Huck - Palo Alto CA
Jonathan K. Ross - Woodinville WA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 1200

US Classification:

711220, 711203, 711216, 711206, 711221, 711202

Abstract:

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A âshort formatâ page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single âlong formatâ page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long.

US Patent:

6408373, Jun 18, 2002

Filed:

May 7, 2001

Appl. No.:

09/850878

Inventors:

Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
Jonathan K. Ross - Sunnyvale CA
William R. Bryg - Saratoga CA
Rajiv Gupta - Los Altos CA
Gary N. Hammond - Campbell CA
Koichi Yamada - San Jose CA

Assignee:

Institute for the Development of Emerging Architectures, LLC - Cupertino CA

International Classification:

G06F 1200

US Classification:

711207, 711209

Abstract:

A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry.

US Patent:

6430670, Aug 6, 2002

Filed:

Nov 1, 2000

Appl. No.:

09/703536

Inventors:

William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
John M. Kessenich - Fort Collins CO
Jonathan K. Ross - Sunnyvale CA
Gary N. Hammond - Campbell CA
Sunil Saxena - Sunnyvale CA
Koichi Yamada - San Jose CA

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711216, 711205, 711206

Abstract:

The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

US Patent:

59408723, Aug 17, 1999

Filed:

Nov 1, 1996

Appl. No.:

8/742467

Inventors:

Gary N. Hammond - Campbell CA
Koichi Yamada - San Jose CA
Stephen G. Burger - Santa Clara CA
James O. Hays - San Jose CA
Jonathan K. Ross - Sunnyvale CA
William R. Bryg - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1210

US Classification:

711207

Abstract:

A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage location in the TLB for storing at least a portion of a second virtual to physical memory translation. The second storage location in the TLB is only software-managed.

US Patent:

6286095, Sep 4, 2001

Filed:

Sep 26, 1995

Appl. No.:

8/533878

Inventors:

Dale C. Morris - Menlo Park CA
Barry J. Flahive - Westford MA
Michael L. Ziegler - Whitinsville MA
Jerome C. Huck - Palo Alto CA
Stephen G. Burger - Santa Clara CA
Ruby B. L. Lee - Los Altos CA
Bernard L. Stumpf - Chelmsford MA
Jeff Kurtze - Nashua NH

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1314

US Classification:

712216

Abstract:

A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.

US Patent:

59151170, Jun 22, 1999

Filed:

Oct 13, 1997

Appl. No.:

8/949295

Inventors:

Jonathan K. Ross - Sunnyvale CA
Jack D. Mills - San Jose CA
James O. Hays - San Jose CA
Stephen G. Burger - Santa Clara CA
Dale C. Morris - Menlo Park CA
Carol L. Thompson - San Jose CA
Rajiv Gupta - Los Altos CA
Stefan M. Freudenberger - Brookline MA
Gary N. Hammond - Campbell CA
Ralph M. Kling - Sunnyvale CA

Assignee:

Institute For The Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 938

US Classification:

395735

Abstract:

The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.

US Patent:

60063254, Dec 21, 1999

Filed:

Dec 19, 1996

Appl. No.:

8/769784

Inventors:

Stephen Burger - Santa Clara CA
Gary N. Hammond - Campbell CA
William R. Bryg - Saratoga CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 938

US Classification:

712214

Abstract:

A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ. d) and an instruction fetch serialization fence instruction (SRLZ. i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.

US Patent:

55155227, May 7, 1996

Filed:

Feb 24, 1994

Appl. No.:

8/201433

Inventors:

K. Monroe Bridges - Fremont CA
William R. Bryg - Saratoga CA
Stephen G. Burger - Santa Clara CA
James M. Hull - Cupertino CA
Michael L. Ziegler - Whitinsville MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

395468

Abstract:

A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.