Stephen E Chambers

US Patent:

6518184, Feb 11, 2003

Filed:

Jan 18, 2002

Appl. No.:

10/051971

Inventors:

Stephen T. Chambers - Portland OR
Valery M. Dubin - Portland OR
Andrew W. Ott - Hillsboro OR
Christine S. Hau-Riege - Milpitas CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438687, 438627, 438634, 438643, 438653, 438682

Abstract:

A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.

US Patent:

6579771, Jun 17, 2003

Filed:

Dec 10, 2001

Appl. No.:

10/013225

Inventors:

Shahriar Ahmed - Portland OR
Mark Bohr - Aloha OR
Stephen Chambers - Portland OR
Richard Green - Aloha OR
Anand Murthy - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218228

US Classification:

438322, 438341, 438360

Abstract:

The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

US Patent:

6703685, Mar 9, 2004

Filed:

Dec 10, 2001

Appl. No.:

10/013075

Inventors:

Shahriar Ahmed - Portland OR
Mark Bohr - Aloha OR
Stephen Chambers - Portland OR
Richard Green - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27082

US Classification:

257565, 257273, 257197, 257370, 257378, 257477, 257511, 257517, 257552, 257556, 257573, 257584, 257591, 257581, 257561, 257560, 257563, 257577, 257578, 257590, 438205, 438213, 438340

Abstract:

The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

US Patent:

6818548, Nov 16, 2004

Filed:

Oct 29, 2002

Appl. No.:

10/283674

Inventors:

Dan S. Lavric - Portland OR
Stephen T. Chambers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438626, 438663, 438675, 438691

Abstract:

A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.

US Patent:

6846752, Jan 25, 2005

Filed:

Jun 18, 2003

Appl. No.:

10/465389

Inventors:

Stephen Chambers - Portland OR, US
Dan S. Lavric - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438771, 438240, 438637

Abstract:

The present invention provides embodiments of methods and devices for the suppression of copper hillocks. Copper hillocks are suppressed by capping the copper layer with a dielectric film before any significant growth of copper hillocks can begin using a ramped temperature dielectric deposition process. Copper hillocks are also suppressed by doping a copper layer with a dopant that will constrain the grain size of the copper during subsequent processing. These methods are applicable to the construction of MIM capacitors and interconnect structures.

US Patent:

7015085, Mar 21, 2006

Filed:

Jul 31, 2003

Appl. No.:

10/632944

Inventors:

Shahriar Ahmed - Portland OR, US
Mark Bohr - Aloha OR, US
Stephen Chambers - Portland OR, US
Richard Green - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/082

US Classification:

438205, 438313, 438340

Abstract:

The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

US Patent:

7064042, Jun 20, 2006

Filed:

Jun 24, 2004

Appl. No.:

10/877749

Inventors:

Shahriar Ahmed - Portland OR, US
Mark Bohr - Aloha OR, US
Stephen Chambers - Portland OR, US
Richard Green - Aloha OR, US
Anand Murthy - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/331

US Classification:

438350, 257565

Abstract:

The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

US Patent:

7135775, Nov 14, 2006

Filed:

Nov 12, 2002

Appl. No.:

10/292326

Inventors:

Stephen T. Chambers - Portland OR, US
Valery M. Dubin - Portland OR, US
Andrew W. Ott - Hillsboro OR, US
Christine S. Hau-Riege - Milpitas CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257762, 257751, 257761, 257763

Abstract:

A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.