Stephen M Conor

US Patent:

6473837, Oct 29, 2002

Filed:

May 18, 1999

Appl. No.:

09/314036

Inventors:

William Alexander Hughes - Burlingame CA
Hebbalalu S. Ramagopal - Austin TX
Derrick R. Meyer - Austin TX
Stephen M. Conor - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711146, 711169, 710 22, 710305

Abstract:

A processor employing a post-cache (LS ) buffer. Loads are stored into the LS buffer after probing the data cache. The load/store unit snoops the loads in the LS buffer against snoop requests received from an external bus. If a snoop invalidate request hits a load within the LS buffer and that load hit in the data cache during its initial probe, the load/store unit scans the LS buffer for older loads which are misses. If older load misses are detected, a synchronization indication is set for the load misses. Subsequently, one of the load misses completes and the load/store unit transmits a synchronization signal with the status for the load miss. The processor synchronizes to the instruction corresponding to the load miss, thereby discarding load hit which was subsequently snoop hit. The discarding instructions are refetched and reexecuted, thereby causing the load hit to reexecute subsequent to an earlier load miss. Load hits may generally proceed ahead of load misses and strong memory ordering rules may still be enforced.