Stephen W Corbin

US Patent:

47501545, Jun 7, 1988

Filed:

Jul 10, 1984

Appl. No.:

6/629349

Inventors:

Brian Lefsky - West Newton MA
Paul K. Rodman - Ashland MA
Stephen S. Corbin - Natick MA

Assignee:

Prime Computer, Inc. - Natick MA

International Classification:

G11C 500

US Classification:

365189

Abstract:

A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

US Patent:

50670719, Nov 19, 1991

Filed:

Feb 27, 1985

Appl. No.:

6/706142

Inventors:

David J. Schanin - Sudbury MA
Russel L. Moore - Hudson MA
John R. Bartlett - Acton MA
Charles S. Namias - Burlington MA
David W. Zopf - Marlboro MA
Brian D. Gill - Londondery NH
Trevor A. Creary - Natick MA
Stephen S. Corbin - Natick MA
Mark J. Matale - Sterling MA
David F. Ford - Boston MA
Steven J. Frank - Westboro MA

Assignee:

Encore Computer Corporation - Fort Lauderdale FL

International Classification:

G06F 946

US Classification:

395275

Abstract:

Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.