Stephen Lloyd Drake

US Patent:

20060242611, Oct 26, 2006

Filed:

Apr 7, 2005

Appl. No.:

11/101138

Inventors:

Stephen Drake - Seattle WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 17/50

US Classification:

716001000

Abstract:

A portion of chip die real estate is allocated to blocks of programmable logic (PL) fabric. These blocks can be used to load special purpose processors which operate in concert with the general purpose processors (GPPs). These processors, implemented in PL, may integrate with a PC system architecture. Blocks of PL are integrated with fixed blocks of logic interfaces connecting, for example, to a system's front side bus. This facilitates configuration of the PL as coprocessors or other devices that may operate as peers to GPPs in the system. Moreover, blocks of PL may be integrated with fixed logic interfaces to existing IO buses within a system architecture. This facilitates configuration of the PL as soft devices, which may appear to the system as physical devices connected to the system. These soft devices can be handled like physical devices connected to the same or similar IO buses.