Stephen E Gilbert

US Patent:

6444542, Sep 3, 2002

Filed:

Apr 3, 2001

Appl. No.:

09/826283

Inventors:

Theodore S. Moise - Los Altos CA
Guoqiang Xing - Plano TX
Mark Visokay - Boise ID
Justin F. Gaynor - San Jose CA
Stephen R. Gilbert - San Francisco CA
Francis Celii - Dallas TX
Scott R. Summerfelt - Cupertino CA
Luigi Colombo - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

438448, 438553

Abstract:

A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

US Patent:

6534809, Mar 18, 2003

Filed:

Dec 19, 2000

Appl. No.:

09/741479

Inventors:

Theodore Moise - Los Altos CA
Stephen R. Gilbert - San Francisco CA
Scott R. Summerfelt - Cupertino CA
Guoqiang Xing - Plano TX
Luigi Colombo - Dallas TX

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01L 2994

US Classification:

257295, 257751

Abstract:

An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material ( of FIG. ); a top electrode formed over the bottom electrode and comprised of a first electrode material ( and of FIG. ); a ferroelectric material ( of FIG. ) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer ( of FIG. ) and a top hardmask layer ( of FIG. ) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

US Patent:

6576922, Jun 10, 2003

Filed:

Dec 21, 2001

Appl. No.:

10/036799

Inventors:

Shawming Ma - Sunnyvale CA
Guoqiang Xing - Plano TX
Stephen R. Gilbert - San Francisco CA

Assignee:

Texas Instruments Incorporated - Dallas TX
Agilent Technologies - Palo Alto CA

International Classification:

H01L 2358

US Classification:

257 48, 257429

Abstract:

Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

US Patent:

6692976, Feb 17, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/650224

Inventors:

Laura Wills Mirkarimi - Sunol CA
Stephen R. Gilbert - San Francisco CA
Guoqiang Xing - Plano TX
Scott Summerfelt - Cupertino CA
Tomoyuki Sakoda - San Jose CA
Ted Moise - Los Altos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA
Texas Instruments, Inc. - Dallas TX

International Classification:

H01L 21306

US Classification:

438 3, 438745, 438750

Abstract:

The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

US Patent:

6709875, Mar 23, 2004

Filed:

Aug 8, 2001

Appl. No.:

09/925201

Inventors:

Stephen R. Gilbert - San Francisco CA
Trace Q. Hurd - Plano TX
Laura W. Mirkarimi - Sunol CA
Scott Summerfelt - Garland TX
Luigi Colombo - Dallas TX

Assignee:

Agilent Technologies, Inc. - Palo Alto CA
Texas Instruments, Inc. - Dallas TX

International Classification:

H01G 706

US Classification:

438 3, 438240

Abstract:

A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e. g. , Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e. g. , Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e. g. , steppers, metrology tools, and the like).

US Patent:

6730354, May 4, 2004

Filed:

Aug 8, 2001

Appl. No.:

09/925223

Inventors:

Stephen R. Gilbert - San Francisco CA
Kaushal Singh - Santa Clara CA
Sanjeev Aggarwal - Plano TX
Stevan Hunter - Fort Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA
Applied Materials, Inc. - Santa Clara CA
Texas Instruments, Inc. - Dallas TX

International Classification:

C23C 1640

US Classification:

42725532, 42725535, 42725536, 427901

Abstract:

Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer uniformity, high throughput and at a relatively low deposition temperature. In one aspect, a source reagent solution comprising a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium is provided. The source reagent solution is vaporized to form a precursor vapor. The precursor vapor is introduced into a chemical vapor deposition chamber containing the substrate. In another aspect, before deposition, the substrate is preheated during a preheating period. After the preheating period, the substrate is disposed on a heated susceptor during a heating period, after which a PZT film is formed on the heated substrate.

US Patent:

6806101, Oct 19, 2004

Filed:

Apr 24, 2003

Appl. No.:

10/422332

Inventors:

Shawming Ma - Sunnyvale CA
Guoqiang Xing - Plano TX
Stephen R. Gilbert - San Francisco CA

Assignee:

Texas Instruments Incorporated - Dallas TX
Agilent Technologies - Palo Alto CA

International Classification:

G01R 3126

US Classification:

438 11, 438 18

Abstract:

Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

US Patent:

6902939, Jun 7, 2005

Filed:

Aug 19, 2002

Appl. No.:

10/223643

Inventors:

Theodore S. Moise - Los Altos CA, US
Guoqiang Xing - Plano TX, US
Mark Visokay - Boise ID, US
Justin F. Gaynor - San Jose CA, US
Stephen R. Gilbert - San Francisco CA, US
Francis Celii - Dallas TX, US
Scott R. Summerfelt - Cupertino CA, US
Luigi Colombo - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/00

US Classification:

438 3, 438680

Abstract:

A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.