Stephen F Greco

US Patent:

6573606, Jun 3, 2003

Filed:

Jun 14, 2001

Appl. No.:

09/881444

Inventors:

Carlos Juan Sambucetti - Croton on Hudson NY
Xiaomeng Chen - Poughkeepsie NY
Birenda Nath Agarwala - Hopewell Juction NY
Chao-Kun Hu - Somers NY
Naftali Eliahu Lustig - Croton on Hudson NY
Stephen Edward Greco - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

257762, 257750, 257751, 257763, 257764, 257765, 257770, 257771, 438612, 438618, 438633, 438687

Abstract:

In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type AâXâY, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

US Patent:

6784105, Aug 31, 2004

Filed:

Apr 9, 2003

Appl. No.:

10/410496

Inventors:

Chih-Chao Yang - Beacon NY
Yun Wang - Hopewell Junction NY
Larry Clevenger - Hopewell Junction NY
Andrew Simon - Fishkill NY
Stephen Greco - Hopewell Junction NY
Kaushik Chanda - Poughkeepsie NY
Terry Spooner - Hopewell Junction NY
Andy Cowley - Wappingers Falls NY

Assignee:

Infineon Technologies North America Corp. - San Jose CA
International Business Machines Corporation - Armonk NY
United Microelectronics Co.

International Classification:

H01L 2144

US Classification:

438687, 438637, 438643, 438653, 438675, 438685, 438688

Abstract:

A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.

US Patent:

7253098, Aug 7, 2007

Filed:

Aug 27, 2004

Appl. No.:

10/711145

Inventors:

Kaushik Arun Kumar - Beacon NY, US
Stephen Edward Greco - LaGrangeville NY, US
Shom Ponoth - Fishkill NY, US
Terry Allen Spooner - New Fairfield CT, US
David L. Rath - Stormville NY, US
Wei-Tsu Tseng - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438637, 438692, 257E21577

Abstract:

A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e. g. , Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

US Patent:

8117568, Feb 14, 2012

Filed:

Sep 25, 2008

Appl. No.:

12/237727

Inventors:

Hua Xiang - Ossining NY, US
Laertis Economikos - Wappingers Falls NY, US
Mohammed F. Fayaz - Pleasantville NY, US
Stephen E. Greco - Lagrangeville NY, US
Patricia A. O'Neil - Newburgh NY, US
Ruchir Puri - Baldwin Place NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716100, 716126, 716132, 703 14

Abstract:

Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

US Patent:

54440157, Aug 22, 1995

Filed:

Apr 11, 1994

Appl. No.:

8/225685

Inventors:

John M. Aitken - Mahopac NY
Klaus D. Beyer - Poughkeepsie NY
Billy L. Crowder - Putnam Valley NY
Stephen E. Greco - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2128

US Classification:

437182

Abstract:

Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

US Patent:

61748145, Jan 16, 2001

Filed:

Apr 25, 2000

Appl. No.:

9/557537

Inventors:

Robert F. Cook - Putnam Valley NY
Eduardo Garcia - Newburgh NY
Nancy A. Greco - Lagrangeville NY
Stephen E. Greco - Lagrangeville NY
Ernest N. Levine - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438692

Abstract:

The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.

US Patent:

47814870, Nov 1, 1988

Filed:

May 4, 1987

Appl. No.:

7/052112

Inventors:

Stephen P. Greco - East Islip NY

Assignee:

Scientific Industries, Inc. - Bohemia NY

International Classification:

B25G 318
F16B 2100

US Classification:

403326

Abstract:

A coupling which includes an inner and outer part is used to connect two coupled members. The inner part has a cylindrical outer wall and the outer part has a recess around which is a cylindrical inner wall, the recess fitting over the inner part so that the outer wall faces the inner wall. A gliding groove in one wall faces an annular locking member on the other wall, and the annular locking member fits into the groove to lock the inner and outer parts in the mounted position. The gliding groove is shaped to glide over the annular locking member during mounting and dismounting. To prevent the inner and outer part from rotating relative to each other, a key on one part fits into a keyway in the other part. The two parts may be connected by applying a slight compressive force so that the gliding groove glides over the annular locking means into the mounted position. Similarly, a slight tensile force may be applied for dismounting.

US Patent:

55302904, Jun 25, 1996

Filed:

Apr 11, 1994

Appl. No.:

8/226103

Inventors:

John M. Aitken - Mahopac NY
Klaus D. Beyer - Poughkeepsie NY
Billy L. Crowder - Putnam Valley NY
Stephen E. Greco - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23528
H01L 23535

US Classification:

257758

Abstract:

Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.