Stephen P Hack

US Patent:

7055035, May 30, 2006

Filed:

Jul 31, 2001

Appl. No.:

09/918974

Inventors:

Michael S Allison - Fort Collins CO, US
Stephen Silva - Fort Collins CO, US
Stephen Patrick Hack - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 9/00

US Classification:

713176, 713 1, 711102

Abstract:

A system and method generate a read only memory (ROM) image for a ROM. The ROM image generator operates with a data image builder. The ROM image generator processes an input file to identify data images for a build. The image identifier generates tokens for building each data image. A data image builder uses the tokens as an input to build each data image. A ROM image builder builds the ROM image using each data image build and generates a data image build validating signature for each data image build, such as a checksum. Once each data image build and associated validating signature is written to the ROM image, the ROM image is completed with a checksum of the entire ROM image.

US Patent:

7523346, Apr 21, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/356560

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richardson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmak - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 7, 714 8, 714 42

Abstract:

Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

US Patent:

7533293, May 12, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/356564

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richardson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmak - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 8, 714710

Abstract:

In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

US Patent:

7568090, Jul 28, 2009

Filed:

Jun 23, 2005

Appl. No.:

11/159757

Inventors:

John A. Morrison - Fort Collins CO, US
Michael S. Allison - Fort Collins CO, US
Stephen P. Hack - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 15/177
G06F 9/24

US Classification:

713 2, 713 1, 713100

Abstract:

Implementations of speedy boot for computer systems are disclosed. In an exemplary embodiment, a method of speedy boot for a computer system may include invoking a platform management interrupt (PMI) to soft reset a processor without resetting hardware for the processor. The method may also include bypassing at least some initialization procedures and tests to speed recovery of the computer system to a usable state. The method may also include resetting operating system interfaces and loading the operating system.

US Patent:

7603582, Oct 13, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/356576

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richardson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmak - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 7, 714 42, 714710

Abstract:

In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

US Patent:

7607038, Oct 20, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/357384

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richarson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmak - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 7, 714 3, 714 10, 714710

Abstract:

In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.

US Patent:

7607040, Oct 20, 2009

Filed:

Feb 17, 2006

Appl. No.:

11/356759

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richardson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmark - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 10, 714 11, 714 25

Abstract:

Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.

US Patent:

7673171, Mar 2, 2010

Filed:

Feb 17, 2006

Appl. No.:

11/356548

Inventors:

Jeff Barlow - Roseville CA, US
Jeff Brauch - Fort Collins CO, US
Howard Calkin - Roseville CA, US
Raymond Gratias - Fort Collins CO, US
Stephen Hack - Fort Collins CO, US
Lacey Joyal - Fort Collins CO, US
Guy Kuntz - Richardson TX, US
Ken Pomaranski - Roseville CA, US
Michael Sedmak - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 8, 714 7

Abstract:

Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.