Stephen J Hale

US Patent:

6442582, Aug 27, 2002

Filed:

Jun 17, 1999

Appl. No.:

09/335351

Inventors:

Stephen C. Hale - San Jose CA

Assignee:

ATI International SRL

International Classification:

G06F 752

US Classification:

708629

Abstract:

A multiplier carry bit compression apparatus and method for a multiplier using Wallace tree addition structures uses a plurality of early and late carry bit compression operations for each level of the Wallace tree addition structure. For each level in a Wallace tree addition structure, each early carry bit compression operation compresses early compression bits prior to each corresponding late carry bit compression operation that compresses late carry bits.

US Patent:

6745318, Jun 1, 2004

Filed:

Aug 18, 1999

Appl. No.:

09/376830

Inventors:

Sanjay Mansingh - Santa Clara CA 95050
Niteen Patkar - Sunnyvale CA 94089
Korbin Van Dyke - Sunol CA 94586
Stephen Hale - San Jose CA 95118
Dee Tovey - Los Gatos CA 95033
Nital Patwa - San Jose CA 95138
Stephen C. Purcell - Mountain View CA 94040

International Classification:

G06F 1710

US Classification:

712 23, 712 32

Abstract:

An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.

US Patent:

6330581, Dec 11, 2001

Filed:

Sep 8, 1998

Appl. No.:

9/149881

Inventors:

Stephen C. Hale - San Jose CA

Assignee:

ATI International SRL - Hastings

International Classification:

G06F 750

US Classification:

708709

Abstract:

The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor includes a first carry-propagate adder that adds a lower 16 bits of a constant or displacement and a lower 16 bits of a segment base, and a second carry-propagate adder connected to the first carry-propagate adder, wherein the second carry-propagate adder adds a lower 16 bits of a base and an output of the first 16-bit carry-propagate adder to generate a lower 16 bits of an address. In one embodiment, the first carry-propagate adder and the second carry-propagate adder are each 16-bit carry-propagate adders.