Stephen B Root

US Patent:

6911827, Jun 28, 2005

Filed:

Oct 21, 2002

Appl. No.:

10/274611

Inventors:

Isaac Kantorovich - Chestnut Hill MA, US
Christopher L. Houghton - Westborough MA, US
Stephen C. Root - Westborough MA, US
James J. St. Laurent - Oakham MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R027/28
G01R023/16

US Classification:

324615, 324 7621, 702 77

Abstract:

A method comprises generating first and second current levels and measuring the first and second current levels. The method further comprises alternately generating the first and second current levels repeatedly to generate a periodic current waveform, and measuring the voltage at at least one port in a system a plurality of times to obtain a plurality of sets of voltage measurements. The plurality of sets of voltage measurements are averaged. The method further comprises alternately generating the first and second current levels repeatedly at a predetermined number of different clock frequencies, determining a Fourier component of the averaged voltage measurements to determine clock frequency-dependent noises, removing the clock frequency-dependent noises to generate a filtered average voltage, and determining an impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.

US Patent:

61638218, Dec 19, 2000

Filed:

Dec 18, 1998

Appl. No.:

9/215354

Inventors:

James B. Keller - Waltham MA
Richard E. Kessler - Shrewsbury MA
Stephen C. Root - Westboro MA
Paul Geoffrey Lowney - Concord MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1320
G06F 1316
G06F 13362

US Classification:

710 57

Abstract:

A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

US Patent:

58023739, Sep 1, 1998

Filed:

Jan 29, 1996

Appl. No.:

8/592982

Inventors:

John S. Yates - Needham MA
Stephen C. Root - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 945

US Classification:

395705

Abstract:

A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process. The non-native image is executed in two different enviroments with first portion executed as an interpreted image and remaining portions as a translated image.