Stephen G Rowland

US Patent:

57940703, Aug 11, 1998

Filed:

Oct 16, 1996

Appl. No.:

8/730777

Inventors:

Jeffrey L. Rabe - Gold River CA
Dave Smyth - Rocklin CA
David D. Lent - Placerville CA
Sathyamurthi Sadhasivan - El Dorado Hills CA
Dahmane Dahmani - Folsom CA
Stephen T. Rowland - Folsom CA
James S. Coke - Cameron Park CA
Mitchell W. Dale - Sacramento CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395842

Abstract:

A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer.

US Patent:

54448573, Aug 22, 1995

Filed:

May 12, 1993

Appl. No.:

8/060804

Inventors:

Stephen T. Rowland - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1338

US Classification:

395309

Abstract:

Peripheral components are interfaced to a computer system through cycle tracking variable delay lines. The computer system includes a system I/O containing, in part, a bus cycle tracking apparatus. The bus cycle tracking apparatus includes cycle tracking logic, a plurality of delay lines, leading and trailing multiplexors (MUXs) and a state MUX. The bus cycle tracking apparatus controls the asynchronous delay of an output reference signal. A plurality of leading and trailing timing reference signals are provided as inputs to the plurality of delay lines. The leading and trailing timing references are delayed by the delay lines a time specified in accordance with an AC timing specification. The bus cycle is tracked such that during a leading/idle state, the leading timing reference is selected as the output reference, and during a trailing state, the trailing reference is selected. The independent control of the output reference signal allows all bus cycle events to be controlled precisely and independently.

US Patent:

55376649, Jul 16, 1996

Filed:

Jan 4, 1996

Appl. No.:

8/582664

Inventors:

Stephen T. Rowland - Folsom CA
Dahmane Dahmani - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1320

US Classification:

395879

Abstract:

A computer system comprising programmable I/O recovery includes a device selection unit, programmable I/O recovery time registers, and a decrementer for specifying I/O recovery times for a plurality of I/O peripheral components. The programmable I/O recovery time registers contain time values, and the time values are programmable by the user of the computer system. The computer system interfaces the I/O peripheral components on an external bus through a plurality of bus cycle signals generated by cycle generation logic. For each I/O bus cycle on the external bus, the device selection unit identifies the I/O device involved in the I/O bus cycle. The device selection unit selects a time value from the programmable I/O recovery time registers corresponding to the I/O device identified, and loads the time value selected in the decrementer. Upon termination of the bus cycle, the device selection unit generates a cycle start signal to enable counting in the decrementer. The decrementer begins to count down from the time value loaded, and when the decrementer reaches a terminal count, a ready signal is generated.