Stephen H Snyder

US Patent:

20210305430, Sep 30, 2021

Filed:

Mar 27, 2020

Appl. No.:

16/833208

Inventors:

- Santa Clara CA, US
Stephen SNYDER - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Urusa ALAAN - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US

International Classification:

H01L 29/78
H01L 29/423
H01L 29/06
H01L 29/165
H01L 29/10
H01L 29/08
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.