Steven Weston Allen

Address:

4069 Riverton Pl, San Diego, CA 92130

Phone:

(858)4812329

VIN:

WBAPH5C50BA443643

Make:

BMW

Model:

3 SERIES

Year:

2011

US Patent:

6909393, Jun 21, 2005

Filed:

Jul 30, 2003

Appl. No.:

10/631450

Inventors:

Ahmad H. Atriss - Chandler AZ, US
Steven P. Allen - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M001/34

US Classification:

341163, 341155

Abstract:

Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.

US Patent:

6967611, Nov 22, 2005

Filed:

Mar 19, 2004

Appl. No.:

10/804453

Inventors:

Ahmad H. Atriss - Chandler AZ, US
Steven P. Allen - Mesa AZ, US
Douglas A. Garrity - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M001/12

US Classification:

341172, 341155, 341161, 341162, 341163

Abstract:

An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

US Patent:

20050260079, Nov 24, 2005

Filed:

May 3, 2005

Appl. No.:

11/121400

Inventors:

Steven Allen - Chandler AZ, US

International Classification:

F04B049/00
F04B017/00

US Classification:

417053000, 417014000, 417012000, 417423100

Abstract:

An electronic pool pump timer that controls the run time of the pump for a period of time each day depending on the date. In the preferred embodiment, the user enters the historical daily maximum and minimum pump run times for the specific pool and the system calculates the required time the pump will run on a given day. The customized run time is thus calculated as a function of the date and the minimum and maximum run times for a given pool. The system then self-adjusts the run time each day as necessary. The device comprises a data input means, a display, memory, and a controller. It may also include a manual override to allow the user to turn the pump on at any time. The device is connected to the pump motor. The device is connected to a power supply and may also include a battery back-up in the event of a power outage. To prevent the pool from freezing, the system may also include an air temperature sensor that triggers pump operation when the ambient air is below a given temperature.

US Patent:

20080029107, Feb 7, 2008

Filed:

Aug 2, 2007

Appl. No.:

11/833109

Inventors:

Bruce Alan Ruff - Chandler AZ, US
Steven Walter Allen - Tempe AZ, US

International Classification:

A24F 1/14
A24D 3/04

US Classification:

131173, 131335

Abstract:

A smoke conditioning and filtration system is disclosed. The system mixes smoke created from a burnable substance, such as tobacco or other herbal substances, with liquid vapor. This causes expanding of the inherent hot gases and moisturizing and cooling of the smoke, thereby creating a more pleasurable smoking experience. The system also conditions the smoke produced from tobacco or other herbal substances by filtering out a portion of the particulates and congeals a portion of the oil contained within the smoke. Furthermore, the system blows smoke from a spout, eliminating the need to put one's mouth on the spout, thus creating a more sanitary smoking experience.

US Patent:

20130321059, Dec 5, 2013

Filed:

May 31, 2012

Appl. No.:

13/484304

Inventors:

Steven P. ALLEN - Chandler AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC - Austin TX

International Classification:

H03L 5/00

US Classification:

327333

Abstract:

A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.

US Patent:

20140002291, Jan 2, 2014

Filed:

Jun 29, 2012

Appl. No.:

13/537308

Inventors:

AHMAD H. ATRISS - Gilbert AZ, US
STEVEN P. ALLEN - Chandler AZ, US
RAKESH SHIWALE - Chandler AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC - Austin TX

International Classification:

H03M 1/12

US Classification:

341172

Abstract:

An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

US Patent:

56063130, Feb 25, 1997

Filed:

Nov 14, 1995

Appl. No.:

8/558619

Inventors:

Steven P. Allen - Mesa AZ
Scott T. Demarest - Gilbert AZ
Thomas R. Troksa - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G08B 522
H04B 700
H04Q 302
H04Q 914

US Classification:

34082554

Abstract:

An electronic tag (10) receives a data message (18) that has a wake-up section (20) followed by a session section (22). The interrogation signal which carries the data message encodes the wake-up section (20) differently from the session section (22). A power manager (28) decodes the wake-up section (20) using a very low power decoder (34) that remains energized during a standby state. When the power manager (28) detects a predetermined identification code (26), it controls a switching circuit (32) to energize a controller (30). The controller (30) may then decode, process, and respond to information conveyed during the session section (22). If the power manager (28) does not detect the identification code (26), the controller (30) remains de-energized. The power manager (28) also includes a synchronizer (38) which determines when a preamble (24) is detected, and an ID decoder (40) that determines when the wake-up section (20) conveys the predetermined identification code (26).

US Patent:

61047260, Aug 15, 2000

Filed:

Mar 31, 1997

Appl. No.:

8/829074

Inventors:

William Chunhung Yip - Scottsdale AZ
Steven Peter Allen - Mesa AZ
James Brian Piket - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04J 322

US Classification:

370468

Abstract:

A technique and method that efficiently and simultaneously transfers both voice and data information over a single communications link (11). The technique and method utilizes a multi-rate vocoder (12) for providing voice information at a plurality of different rates. Accordingly, the vocoder may be dynamically adjusted during transfer of information to meet channel bandwidth requirements. The technique and method also utilizes a bit-control protocol for inserting voice information within a stream of data information by the use of inserting flags having predetermined bitstreams. Accordingly, voice information is dynamically inserted into an existing bitstream of data information such that voice information is transferred only upon demand and when needed. This prevents the transfer of useless information, such as voice information when a speaker is silent and, thus, allows for very efficient utilization of system bandwidth.