Steven R Bird

US Patent:

7757196, Jul 13, 2010

Filed:

Apr 4, 2007

Appl. No.:

11/696666

Inventors:

Steven C. Bird - San Jose CA, US
Linda M. Mazaheri - Los Gatos CA, US
Bob Needham - San Jose CA, US
Phuong Rosalynn Duong - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 12, 716 7, 716 13, 716 14, 716 15

Abstract:

Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

US Patent:

7797663, Sep 14, 2010

Filed:

Apr 4, 2007

Appl. No.:

11/696659

Inventors:

Steven C. Bird - San Jose CA, US
Varoujan Malian - San Jose CA, US
Mudasir Ahmad - Santa Clara CA, US
Charles H. Casale - San Jose CA, US
Danlu Tang - Cupertino CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 15, 716 1, 716 4

Abstract:

Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

US Patent:

7979983, Jul 19, 2011

Filed:

Apr 4, 2007

Appl. No.:

11/696670

Inventors:

Steven C. Bird - San Jose CA, US
Linda M. Mazaheri - Los Gatos CA, US
Bob Needham - San Jose CA, US
Phuong Rosalynn Duong - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H01K 3/10
H05K 1/11

US Classification:

29852, 29832, 29831, 29846, 29847, 174262

Abstract:

Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

US Patent:

8344266, Jan 1, 2013

Filed:

Aug 10, 2007

Appl. No.:

11/837322

Inventors:

Steven C. Bird - San Jose CA, US
Linda M. Mazaheri - Los Gatos CA, US
Bob Needham - San Jose CA, US
Phuong Rosalynn Duong - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H05K 1/11

US Classification:

174262, 174260

Abstract:

Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

US Patent:

20100270681, Oct 28, 2010

Filed:

Jul 12, 2010

Appl. No.:

12/834488

Inventors:

Steven C. Bird - San Jose CA, US
Linda M. Mazaheri - Los Gatos CA, US
Bob Needham - San Jose CA, US
Phuong Rosalynn Duong - San Jose CA, US

International Classification:

H01L 23/498
G06F 17/50

US Classification:

257773, 716127, 716126, 716137, 257E23068

Abstract:

Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

US Patent:

47558873, Jul 5, 1988

Filed:

Oct 31, 1986

Appl. No.:

6/925346

Inventors:

Phillip E. Deaver - Cupertino CA
Stephen K. Will - Sunnyvale CA
Steven C. Bird - San Jose CA
Mark S. Allen - Saratoga CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11B 500
G11B 3100

US Classification:

360 5

Abstract:

A drop out trigger captures waveform data when a normally continuous input signal is disrupted or interrupted. In the preferred embodiment, a conventional trigger detects a parameter periodically satisfied by the continuous signal and resets a timer whenever a trigger event occurs. The alarm count of the timer is set for an interval slightly larger than the periodic interval. If the timer reaches the alarm count, a measurement signal is generated.

US Patent:

20200068706, Feb 27, 2020

Filed:

Nov 4, 2019

Appl. No.:

16/673719

Inventors:

- Sunnyvale CA, US
Steven C. Bird - San Jose CA, US

International Classification:

H05K 1/02
G02B 6/42
H05K 3/46
H05K 1/03
H05K 1/11
G02B 6/132
G02B 6/124
G02B 6/122
G02B 6/12
G02B 6/136
H01P 3/08
H05K 1/09

Abstract:

An optical waveguide is disclosed. In a disclosed embodiment, the optical waveguide includes a first aluminum nitride (AlN) thin film disposed on a layer of high-frequency polymer. A second AlN thin film is embedded in the first AlN thin film. In disclosed embodiments, the nitrogen concentration level of the first AlN thin film is different than the concentration level of the second AlN thin film.

US Patent:

20160323992, Nov 3, 2016

Filed:

Apr 25, 2016

Appl. No.:

15/138116

Inventors:

- Sunnyvale CA, US
Steven C. Bird - San Jose CA, US

International Classification:

H05K 1/02
H05K 1/11
G02B 6/12
H05K 1/09
G02B 6/122
G02B 6/136
H05K 1/03
H01P 3/08

Abstract:

A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.