Steven Y Cheng

US Patent:

7873803, Jan 18, 2011

Filed:

Sep 25, 2007

Appl. No.:

11/861146

Inventors:

Steven S. Cheng - Sunnyvale CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711161, 711103, 711162, 711E12103, 714 6

Abstract:

A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern.

US Patent:

7953930, May 31, 2011

Filed:

Dec 7, 2007

Appl. No.:

11/952744

Inventors:

Steven S. Cheng - Sunnyvale CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G06F 13/00

US Classification:

711115, 711103, 711E12008

Abstract:

A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.

US Patent:

7971023, Jun 28, 2011

Filed:

Apr 30, 2008

Appl. No.:

12/112204

Inventors:

Steven S. Cheng - Sunnyvale CA, US
Stephen Tam - Fremont CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711170, 711104, 711154, 711167

Abstract:

In order to maintain a memory system's performance levels to its end-of-life, latency threshold level(s) are specified and associated with different memory system operating parameters. In one embodiment, the memory system monitors and gathers performance statistics in real time, and in accordance with specific memory transfer sizes. A current latency level can be dynamically calculated using the performance statistics and compared to previously established latency threshold levels. If the current latency level is greater than or equal to a specific latency threshold level, the memory system's configuration setting can be adjusted according to the operating parameters associated with the latency threshold level to offset the increased latency.

US Patent:

8144496, Mar 27, 2012

Filed:

Jun 30, 2009

Appl. No.:

12/495717

Inventors:

Steven Cheng - Sunnyvale CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/04

US Classification:

365 63, 36518505

Abstract:

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

US Patent:

8161231, Apr 17, 2012

Filed:

Mar 7, 2011

Appl. No.:

13/042043

Inventors:

Steven S. Cheng - Sunnyvale CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G06F 12/00

US Classification:

711103, 711115, 711E12008

Abstract:

A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.

US Patent:

8406076, Mar 26, 2013

Filed:

Jun 28, 2010

Appl. No.:

12/824703

Inventors:

Steven S. Cheng - Sunnyvale CA, US
Peter Hwang - Newark CA, US
Annie C. Chang - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 11/413

US Classification:

365227

Abstract:

A method and apparatus for reducing power consumption during an operation in a non-volatile storage device is disclosed. A non-volatile storage device controller that is in communication with a non-volatile memory in the non-volatile storage device receives a characteristic corresponding to a time duration required for the non-volatile memory to complete an operation. The controller disables a circuit that indicates when an operation by the non-volatile memory is complete. The controller then initiates the operation in the non-volatile memory, and maintains the circuit in a disabled state for a first predetermined time that is a portion of the time duration. The controller enables the circuit upon expiration of the first predetermined time and prior to the completion of the operation. The controller receives an indication of the completion of the operation via the circuit.

US Patent:

8413015, Apr 2, 2013

Filed:

Sep 21, 2009

Appl. No.:

12/563455

Inventors:

Steven S. Cheng - Sunnyvale CA, US
Aruna Gutta - San Jose CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 29/00

US Classification:

714763

Abstract:

A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.

US Patent:

8488356, Jul 16, 2013

Filed:

Mar 26, 2012

Appl. No.:

13/430548

Inventors:

Steven Cheng - Sunnyvale CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 5/06

US Classification:

365 63, 36518503

Abstract:

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.