Gopro
Senior Camera System Firmware Engineer
On Semiconductor Jul 2016 - May 2017
Senior Software Engineer
Intel Corporation Apr 2014 - Jun 2016
Senior Software Engineer, Intel
Qualcomm Feb 2013 - Apr 2014
Senior Software Engineer
Education:
Southeast University
Masters, Electronics Engineering
Skills:
Camera System and Image Quality C/C++ and Matlab Ubuntu Embeded Firmware Windows Software Camera Sensor Driver Audio Device Driver Video and Audio on Internet and Wifi Image Processing
Fosun Group - Shanghai, China since Sep 2012
Fund Manager
CCG Investor Relations - Greater Los Angeles Area Mar 2010 - Jun 2012
Financial Analyst/Writer
CCG Investor Relations Apr 2009 - Feb 2010
Investor Relations Intern
China Jianyin Investment Securities Feb 2008 - Mar 2008
Analyst Intern
Bank of China Jul 2006 - Aug 2006
Accounting Intern
Education:
Pepperdine University, The George L. Graziadio School of Business and Management 2008 - 2009
Master, Finance
Tianjin University of Finance and Economics 2004 - 2008
Bachelor, Finance
Interests:
Photography
Languages:
English Cantonese Mandarin Hunanese
Us Patents
Extended Page Mode With Memory Address Translation Using A Linear Shift Register
Frank Yuhhaw Wu - Fremont CA Steven K. Feng - Cupertino CA
Assignee:
Seagate Technology, Inc. - Scotts Valley CA
International Classification:
G06F 1206
US Classification:
711217
Abstract:
The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed.