Steven C Hobbs

US Patent:

6675374, Jan 6, 2004

Filed:

Oct 12, 1999

Appl. No.:

09/416436

Inventors:

John Samuel Pieper - Mont Vernon NH
Steven Orodon Hobbs - Westford MA
Stephen Corridon Root - Westboro MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 945

US Classification:

717141, 717131, 717142, 717154, 712235, 712237

Abstract:

A technique is provided for inserting memory prefetch instructions only at appropriate locations in program code. The instructions are inserted into the program code such that, when the code is executed, the speed and efficiency of execution of the code may be improved, cache conflicts arising from execution of the prefetch instruction may be substantially eliminated, and the number of simultaneously-executing memory prefetch operations may be limited to prevent stalling and/or overtaxing of the processor executing the code.

US Patent:

56131178, Mar 18, 1997

Filed:

Apr 20, 1994

Appl. No.:

8/231441

Inventors:

Caroline S. Davidson - Hollis NH
Richard B. Grove - Westford MA
Steven O. Hobbs - Westford MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 300
G06F 500

US Classification:

395708

Abstract:

A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation function of the back end may be targeted for any of a number of computer architectures. A front end is tailored for each different source language, such as Cobol, Fortran, Pascal, C, C++, etc. The front end scans and parses the source code modules, and generates from them an intermediate language representation of the source code programs expressed in the source code. The intermediate language represents any of the source code languages in a universal manner, so the interface between the front end and back end is of a standard format, and need not be rewritten for each language-specific front end. A feature is a method for doing code generation using code templates in a multipass manner. The selection and application of code templates occurs at four different times during the compilation process: (1) A pattern select phase does a pattern match in a context pass to select the best code templates; (2) Tasks of the context pass use context actions of the selected templates to analyze the evaluation order to expressions and to allocate temporary names; (3) A bind pass uses the binding actions of the selected templates to allocate template names; (4) Finally, a code pass uses code generation actions of the selected templates to guide the generation of object code.

US Patent:

54936756, Feb 20, 1996

Filed:

May 26, 1994

Appl. No.:

8/249670

Inventors:

Robert N. Faiman - Wilton NH
David S. Blickstein - Hudsoon NH
Steven O. Hobbs - Westford MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 300
G06F 500

US Classification:

395700

Abstract:

A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation function of the back end may be targeted for any of a number of computer architectures. A front end is tailored for each different source language, such as Cobol, Fortran, Pascal, C, C++, etc. The front end scans and parses the source code modules, and generates from them an intermediate language representation of the source code programs expressed in the source code. The intermediate language represents any of the source code languages in a universal manner, so the interface between the front end and back end is of a standard format, and need not be rewritten for each language-specific front end. A feature is a mechanism for representing effects and dependencies in the interface between front end and back end. An element has an effect if it writes to memory, and has a dependency if it reads from a location which some other node may write to.

US Patent:

56279817, May 6, 1997

Filed:

Jul 1, 1994

Appl. No.:

8/270192

Inventors:

Michael C. Adler - Lexington MA
Steven O. Hobbs - Westford MA
Paul G. Lowney - Concord MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 938

US Classification:

395582

Abstract:

Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.

US Patent:

50438670, Aug 27, 1991

Filed:

Mar 18, 1988

Appl. No.:

7/170393

Inventors:

Dileep P. Bhandarkar - Shrewsbury MA
Robert Supnik - Carlisle MA
Steven Hobbs - Westford MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A data process system capable of executing vector instructions and scalar instructions detects the occurrence of arithmetic exception conditions and allows subsequent scalar instruction processing until execution of the next vector instruction is required.

US Patent:

59238631, Jul 13, 1999

Filed:

Oct 25, 1995

Appl. No.:

8/548114

Inventors:

Michael C. Adler - Lexington MA
Steven O. Hobbs - Westford MA
Paul Geoffrey Lowney - Concord MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 938

US Classification:

395392

Abstract:

Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.

US Patent:

56340230, May 27, 1997

Filed:

Jul 1, 1994

Appl. No.:

8/270184

Inventors:

Michael C. Adler - Lexington MA
Steven O. Hobbs - Westford MA
Paul G. Lowney - Concord MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 930
G06F 1516

US Classification:

395591

Abstract:

Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine in the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of a eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handing routine if the semaphore indicates that an exception occurred when the speculative instruction was executed, and the predicate is true, which indicates that the speculative instruction was properly executed.

US Patent:

51971380, Mar 23, 1993

Filed:

Dec 26, 1989

Appl. No.:

7/457144

Inventors:

Steven O. Hobbs - Westford MA
Hai Huang - Nashua NH

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 900
G06F 946
G06F 1516
G06F 15347

US Classification:

395375

Abstract:

Save-Exception-State and Restore-Exception-State primitives are defined in the operating system and are used to confine the reporting of delayed asynchronous coprocessor exceptions to the respective code threads that generate the exceptions. The Save-Exception-State primitive saves the coprocessor exception state pertinent to the currently executed code thread, and the Restore-Exception-State primitive restores a selected one of the exception states having been saved. The Save-Exception-State primitive synchronizes the coprocessor, disables use of the coprocessor, saves any pending coprocessor exception state into memory, and clears the coprocessor exception state information from the coprocessor or a "thread descriptor" area of memory allocated to the current code thread. The Restore-Exception-State primitive synchronizes the coprocessor, disables use of the coprocessor, reports any pending exceptions in the coprocessor, and restores the saved exception state into a respective code thread descriptor in memory allocated to the code thread having generated the saved exception state information. The restored exception state is reported by a "Coprocessor-Disabled" exception handler that checks for any exceptions pending in the coprocessor or thread descriptor, when necessary stores the coprocessor state information from the process which last executed a coprocessor instruction, when necessary retrieves the coprocessor state information for the current process, reports any pending exceptions, and reenables use of the coprocessor.