Steven P Krueger

US Patent:

6449692, Sep 10, 2002

Filed:

Dec 15, 1998

Appl. No.:

09/212034

Inventors:

Steven D. Krueger - Dallas TX
Jonathan H. Shiell - Plano TX
Ian Chen - Santa Clara CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1208

US Classification:

711122, 711207, 711133, 711129, 345543, 345544, 345568

Abstract:

A computer system ( ) comprising a central processing unit ( ) and a memory hierarchy. The memory hierarchy comprises a first cache memory ( ) and a second cache memory ( ). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information ( ) and pixel data ( ). Lastly, the computer system comprises cache control circuitry ( ) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

US Patent:

6539467, Mar 25, 2003

Filed:

Oct 31, 2000

Appl. No.:

09/703105

Inventors:

Timothy D. Anderson - Dallas TX
David Hoyle - Glendale AZ
Donald E. Steiss - Richardson TX
Steven D. Krueger - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

711219, 711201, 711149

Abstract:

A data processing system ( ) is provided with a digital signal processor (DSP) ( ) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (. D ,. D ) connected to dual memory ports (T , T ) in a level one data cache memory controller ( ). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

US Patent:

6629187, Sep 30, 2003

Filed:

Oct 31, 2000

Appl. No.:

09/702477

Inventors:

Steven D. Krueger - Dallas TX
David A. Comisky - St. Charles IL

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1208

US Classification:

711 3, 711 1, 711118, 711130, 711144, 711147, 711209

Abstract:

A digital system is provided with a microprocessor ( ), a cache ( ) and various memory and devices ( ). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) ( ). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit ( ) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.

US Patent:

6775750, Aug 10, 2004

Filed:

May 8, 2002

Appl. No.:

10/141661

Inventors:

Steven D. Krueger - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

711152, 711163, 710200

Abstract:

A method and apparatus is provided for operating a digital system having several processors ( ) and peripheral devices ( ) connected to a shared memory subsystem ( ). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) ( ). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region. Access to the identified region is allowed to an initiator resource only if the resource has access rights to the identified region, otherwise an error process is initiated ( ).

US Patent:

7725678, May 25, 2010

Filed:

Feb 17, 2005

Appl. No.:

11/060208

Inventors:

Steven Krueger - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9/00

US Classification:

712 4

Abstract:

A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation index vector. An index vector generation circuit is also disclosed.

US Patent:

20030120900, Jun 26, 2003

Filed:

Aug 21, 2002

Appl. No.:

10/225034

Inventors:

Eric Stotzer - Houston TX, US
Steven Krueger - Dallas TX, US
Timothy Anderson - Dallas TX, US

International Classification:

G06F009/30

US Classification:

712/215000

Abstract:

A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. A second software pipeline loop procedure can be initiated prior to the completion of first software pipeline loop procedure.

US Patent:

20120017067, Jan 19, 2012

Filed:

Jul 13, 2010

Appl. No.:

12/835320

Inventors:

Jagadeesh SANKARAN - Allen TX, US
Joseph R. ZBICIAK - Arlington TX, US
Steven D. KRUEGER - Dallas TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06F 9/30
G06F 15/76
G06F 9/02
G06F 9/312

US Classification:

712 24, 712205, 712208, 712E09002, 712E09028, 712E09033

Abstract:

In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

US Patent:

20130046934, Feb 21, 2013

Filed:

Aug 15, 2011

Appl. No.:

13/209439

Inventors:

Robert Nychka - Canton TX, US
William Michael Johnson - Austin TX, US
Steven D. Krueger - Dallas TX, US

International Classification:

G06F 12/08

US Classification:

711119, 711118, 711E12023, 711E12017

Abstract:

A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.