Steven Charles Krueger

US Patent:

20030120900, Jun 26, 2003

Filed:

Aug 21, 2002

Appl. No.:

10/225034

Inventors:

Eric Stotzer - Houston TX, US
Steven Krueger - Dallas TX, US
Timothy Anderson - Dallas TX, US

International Classification:

G06F009/30

US Classification:

712/215000

Abstract:

A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. A second software pipeline loop procedure can be initiated prior to the completion of first software pipeline loop procedure.

US Patent:

59826940, Nov 9, 1999

Filed:

Nov 8, 1996

Appl. No.:

8/747120

Inventors:

Wilbur Christian Vogley - Missouri City TX
Anthony Michael Balistreri - Houston TX
Karl M. Guttag - Missouri City TX
Steven D. Krueger - Houston TX
Joseph H. Neal - Sugarland TX
Kenneth A. Poteet - Houston TX
Joseph P. Hartigan - Stafford TX
Roger D. Norwood - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

365221

Abstract:

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

US Patent:

59128542, Jun 15, 1999

Filed:

Aug 4, 1997

Appl. No.:

8/905751

Inventors:

Wilbur Christian Vogley - Missouri City TX
Anthony Michael Balistreri - Houston TX
Karl M. Guttag - Missouri City TX
Steven D. Krueger - Houston TX
Joseph H. Neal - Sugarland TX
Kenneth A. Poteet - Houston TX
Joseph P. Hartigan - Stafford TX
Roger D. Norwood - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

365221

Abstract:

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

US Patent:

58089586, Sep 15, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/477735

Inventors:

Wilbur Christian Vogley - Missouri City TX
Anthony Michael Balistreri - Houston TX
Karl M. Guttag - Missouri City TX
Steven D. Krueger - Houston TX
Joseph H. Neal - Sugarland TX
Kenneth A. Poteet - Houston TX
Joseph P. Hartigan - Stafford TX
Roger D. Norwood - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800

US Classification:

365233

Abstract:

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

US Patent:

55879543, Dec 24, 1996

Filed:

Oct 21, 1994

Appl. No.:

8/327540

Inventors:

Wilbur C. Vogley - Missouri City TX
Anthony M. Balistreri - Houston TX
Karl M. Guttag - Missouri City TX
Steven D. Krueger - Houston TX
Joseph H. Neal - Sugarland TX
Kenneth A. Poteet - Houston TX
Joseph P. Hartigan - Stafford TX
Roger D. Norwood - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

365221

Abstract:

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

US Patent:

49625330, Oct 9, 1990

Filed:

Feb 17, 1989

Appl. No.:

7/312142

Inventors:

Steven D. Krueger - Houston TX
Martha A. Branstad - Gaithersburg MD
Stephen T. Walker - Glenwood MD

Assignee:

Texas Instrument Incorporated - Dallas TX

International Classification:

H04L 900

US Classification:

380 25

Abstract:

A computer system uses security labels for evey word in memory. Each access to a memory location requires that the security level of the memory location be compared to that of a process which is making the access. If the security level of the process does not dominate that of the memory location, access is denied. Each time a memory location is modified, it is assigned a security level consistent with the levels of all of the data which was used to modify the memory location.

US Patent:

55985408, Jan 28, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/475244

Inventors:

Steven D. Krueger - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 122

US Classification:

395284

Abstract:

A computer includes a processor for processing data, and memory modules for storing the data. Each memory module includes a read-write memory and a configuration memory. The configuration memory (i) contains memory module characteristic information, (ii) is adapted for storing a sequence of binary data values, accessing the stored binary data only in sequential order, and only at the first data value or the next data value, and (iii) has a NEXT signal pin. The configuration memory is adapted for receiving at the NEXT signal pin, and responding to, a CAS signal used by standard DRAMs. In other features of the invention, the memory module characteristic information includes an identification code for the manufacturer of the memory module, a part number for the memory module, the depth of the memory, access times to read full and page, and delay times to read and write full and page.

US Patent:

53901495, Feb 14, 1995

Filed:

Jan 21, 1994

Appl. No.:

8/184749

Inventors:

Wilbur C. Vogley - Missouri City TX
Anthony M. Balistreri - Houston TX
Karl M. Guttag - Missouri City TX
Steven D. Krueger - Houston TX
Joseph H. Neal - Sugarland TX
Kenneth A. Poteet - Houston TX
Joseph P. Hartigan - Stafford TX
Roger D. Norwood - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

36518901

Abstract:

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.