Steven James Mcclure

US Patent:

6687903, Feb 3, 2004

Filed:

Jun 28, 2000

Appl. No.:

09/605626

Inventors:

Steven R. Chalmer - Weston MA
Steven T. McClure - Northboro MA
Brett D. Niver - Waltham MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 400

US Classification:

718100, 718102

Abstract:

Disclosed is inhibiting process starvation in a multitasking operating system by providing a first type of scheduling event at periodic timer intervals, providing a second type of second scheduling event in response to a running processes voluntarily relinquishing the processor, and, in response to a scheduling event, replacing an old process with a new process only if the old process has run for more than a predetermined amount of time. The predetermined amount of time may be one half of the timer interval. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Mass. The core kernel code may be written for the general target platform, such as the PowerPC architecture. Since the PowerPC implementation specific modules are well defined, the system may be quite portable between PowerPC processors (such as the 8260 and 750), and should prove relatively easy to port to any PowerPC based Symmetrix adapter board/CPU combination.

US Patent:

6728962, Apr 27, 2004

Filed:

Jun 28, 2000

Appl. No.:

09/605172

Inventors:

Steven R. Chalmer - Weston MA
Steven T. McClure - Northboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 900

US Classification:

718108, 711207, 711208, 712228

Abstract:

Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context information for a plurality of processes, providing an array of pointers to the context blocks, providing an index to the array of pointers, and swapping context by adjusting at least one pointer in the array of pointers to point to a context block of a new process. Further included may be incrementing the index prior to adjusting the at least one pointer in the array of pointers. Further included may be, after adjusting at least one pointer in the array of pointers, decrementing the index and causing the processor to jump to an address indicated by a program counter value of the new process. The context information may include values for registers, a stack pointer, and a program counter for a process. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Mass.

US Patent:

6757790, Jun 29, 2004

Filed:

Feb 19, 2002

Appl. No.:

10/078923

Inventors:

Steven R. Chalmer - Weston MA
Steven T. McClure - Northboro MA
Brett D. Niver - Grafton MA
Richard G. Wheeler - Belmont MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1200

US Classification:

711147, 711118, 711141, 711142, 711143, 711144, 711145, 711146, 711148, 709212, 709213, 709214, 709215, 709216

Abstract:

The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.

US Patent:

7296271, Nov 13, 2007

Filed:

Jun 28, 2000

Appl. No.:

09/605812

Inventors:

Steven R. Chalmer - Weston MA, US
Steven T. McClure - Northboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 9/46
G06F 9/40
G06F 9/44

US Classification:

718108, 718100, 718102, 712202, 712228

Abstract:

Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address corresponding to code of the particular one of the schedulers, and the processor executing code at an address corresponding to the program counter. Also included may be setting a stack pointer to an address corresponding to stack space for the particular one of the schedulers and the processor using the stack space at the stack pointer after executing code at the address corresponding to the program counter. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Ma. The core kernel code may be written for the general target platform, such as the PowerPC architecture. Since the PowerPC implementation specific modules are well defined, the system may be quite portable between PowerPC processors (such as the 8260 and 750), and should prove relatively easy to port to any PowerPC based Symmetrix adapter board/CPU combination.

US Patent:

7302526, Nov 27, 2007

Filed:

Mar 29, 2004

Appl. No.:

10/811566

Inventors:

Jerome J. Cartmell - Natick MA, US
Qun Fan - Boston MA, US
Steven T. McClure - Northboro MA, US
Robert DeCrescenzo - Franklin MA, US
Haim Kopylovitz - Newton MA, US
Eli Shagam - Brookline MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/16

US Classification:

711120, 711162, 714 6, 714 7

Abstract:

Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of mirrored memories, determining that hardware corresponding to the faulting memory of the pair of mirrored memories has been successfully replaced to provide a new memory, in response to the new memory being provided, causing data to be copied from the non-faulting memory to the new memory while data is being read to and written from the non-faulting memory, and, in response to successful copying to the new memory, causing writes to be performed to both memories of the pair of mirrored memories and selecting one of the pair of mirrored memories for read operations when one or more read operations are performed. Handling a faulting memory may also include, in response to a write being performed to the non-faulting memory while data is being copied from the non-faulting memory to the new memory, causing the write to be performed to the non-faulting memory and the new memory.

US Patent:

7472221, Dec 30, 2008

Filed:

Mar 29, 2004

Appl. No.:

10/812291

Inventors:

Jerome J. Cartmell - Natick MA, US
Qun Fan - Boston MA, US
Steven T. McClure - Northboro MA, US
Robert DeCrescenzo - Franklin MA, US
Haim Kopylovitz - Newton MA, US
Eli Shagam - Brookline MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00

US Classification:

711104, 711162

Abstract:

Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.

US Patent:

8090789, Jan 3, 2012

Filed:

Jun 28, 2007

Appl. No.:

11/769745

Inventors:

John O'Shea - Newton MA, US
Jeffrey Kinne - Needham MA, US
Michael Sgrosso - Franklin MA, US
Steven T. McClure - Northboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16

US Classification:

709211

Abstract:

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

US Patent:

8375174, Feb 12, 2013

Filed:

Mar 29, 2010

Appl. No.:

12/798035

Inventors:

Jerome Cartmell - Natick MA, US
Steven McClure - Northboro MA, US
Alesia Tringale - Worcester MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00

US Classification:

711148, 711147, 711153, 711170, 711173, 711E12084

Abstract:

Described are techniques for partitioning memory. A plurality of boards is provided. Each of the plurality of boards includes a physical memory portion and a set of one or more processor. The physical memory portion in each of said plurality of boards is partitioned into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board. Each of the one or more other memory partitions not being accessible to a processor on a board other than said each board.