Steven K Molnar

US Patent:

6731024, May 4, 2004

Filed:

Oct 21, 2002

Appl. No.:

10/274481

Inventors:

Steven A. Molnar - Golden CO 80403
Virginia A. Molnar - Golden CO 80403

International Classification:

H01B 730

US Classification:

307147, 307 38, 307116

Abstract:

A power strip having a plurality of grounded outlet receptacles includes a motion sensor circuit. The motion sensor circuit controls operation of the power strip, and hence, operation of all electronic components plugged into the power strip.

US Patent:

7286134, Oct 23, 2007

Filed:

Dec 17, 2003

Appl. No.:

10/740229

Inventors:

James M. Van Dyke - Austin TX, US
John S. Montrym - Cupertino CA, US
Steven E. Molnar - Chapel Hill NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/02
G06T 9/00
G06T 15/40

US Classification:

345544, 345555, 345421

Abstract:

A tiled graphics memory permits z data and stencil data to be stored in different portions of a tile. The tile may be further divided into data sections, each of which may have a byte size corresponding to a memory access size.

US Patent:

7519797, Apr 14, 2009

Filed:

Nov 2, 2006

Appl. No.:

11/556020

Inventors:

Gregory J. Stiehl - Austin TX, US
David L. Anderson - Durham NC, US
Cass W. Everitt - Round Rock TX, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US

Assignee:

NIVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/00
G06F 15/76

US Classification:

712227, 712 4, 712225

Abstract:

An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is reported asynchronously to a global counter. The global counter is configured to be of higher precision than the local counter and is positioned at a place that is convenient for reporting the events, e. g. , at the end of the graphics pipeline.

US Patent:

8627041, Jan 7, 2014

Filed:

Oct 8, 2010

Appl. No.:

12/901452

Inventors:

David B. Glasco - Austin TX, US
Peter B. Holmqvist - Cary NC, US
George R. Lynch - Raleigh NC, US
Patrick R. Marchand - Apex NC, US
Karan Mehra - Cary NC, US
James Roberts - Austin TX, US
Cass W. Everitt - Heath TX, US
Steven E. Molnar - Chapel Hill NC, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711208, 711100, 711114, 711118, 711141, 711154, 711200, 711206

Abstract:

One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.