Steven D Riley

US Patent:

6944189, Sep 13, 2005

Filed:

Aug 30, 2001

Appl. No.:

09/943781

Inventors:

Philip J. Pines - Palo Alto CA, US
Steven Riley - Summerland CA, US

Assignee:

Verilink Corporation - Madison AL

International Classification:

H04J003/06

US Classification:

370503, 370516, 375356

Abstract:

A method of providing improved accuracy of the calculation of the long-term average arrival rate (AAR) of an ATM packet stream is disclosed. Using this method, accurate synchronization of a receiver clock to a network clock is achieved. The invention measures the variable time interval, T, required to complete the arrival of a known and fixed number of data packets, C. Using a predetermined and relatively large number of data packets, a time interval measurement is accurately measured to very precise values. Because the time interval measurement is triggered precisely by the arrival of the first data packet to the complete arrival of the last data packet in the session, there is no quantization error with respect to the first and last data packet. AAR is then calculated as (C*S)/T, where S is the number of samples per data packet.

US Patent:

20140123094, May 1, 2014

Filed:

Oct 31, 2012

Appl. No.:

13/665760

Inventors:

- San Jose CA, US
Arnold Ginetti - Antibes, FR
Thomas Jordan - Pittsburgh PA, US
Jose A. Martinez - Pittsburgh PA, US
Jeffrey Markham - San Jose CA, US
Steven Riley - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716126

Abstract:

A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.