Steven A Roberts

US Patent:

6438556, Aug 20, 2002

Filed:

Dec 11, 1998

Appl. No.:

09/210503

Inventors:

Nadeem Malik - Austin TX
Jason Raymond Baumgartner - Austin TX
Steven Leonard Roberts - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1730

US Classification:

707101, 707 6, 707100, 386109, 386111, 386112, 3484191, 3483841

Abstract:

A system and method for compressing data on a computer system is disclosed. The method and system include separating the data into a plurality of segments. The plurality of segments includes a plurality of unique segments. The method and system also include providing a plurality of code words. Each of the plurality of code words corresponds to a unique segment of the plurality of unique segments. The method and system also include providing a representation of the data. The representation includes the plurality of code words for the plurality of segments. The plurality of code words in the representation replaces the plurality of segments. As a result, the data in the representation could be accessed randomly.

US Patent:

6449752, Sep 10, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/404278

Inventors:

Jason Raymond Baumgartner - Austin TX 78728
Nadeem Malik - Austin TX 78750
Steven Leonard Roberts - Austin TX 78746

International Classification:

G06F 1750

US Classification:

716 5

Abstract:

A method for automatically generating a set of specifications against which a model of the digital circuit can be verified. In one embodiment, the method includes an initial step in which a specification class that corresponds to a type of behavior of the digital circuit is defined. A set of specification formulae that satisfies the defined specification class is then enumerated. Each formula in the set of formulae is then applied to the model of the digital circuit to determine whether the digital circuit satisfies the corresponding formula. The definition of the specification class preferably includes a set of input conditions, a set of output or response conditions, and a temporal component. Preferably, the enumeration of the specification formulae includes all specification formulae that satisfy the specification class. The application of the set of formulae to the model of the digital circuit is preferably achieved with a verification engine such as a model checker.

US Patent:

6463412, Oct 8, 2002

Filed:

Dec 16, 1999

Appl. No.:

09/464847

Inventors:

Jason Raymond Baumgartner - Austin TX
Steven Leonard Roberts - Austin TX
Nadeem Malik - Austin TX
Flemming Andersen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G10L 1300

US Classification:

704246, 704261, 704269

Abstract:

A high performance voice transformation apparatus and method is provided in which voice input is transformed into a symbolic representation of phonemes in the voice input. The symbolic representation is used to retrieve output voice segments of a selected target speaker for use in outputting the voice input in a different voice. In addition, voice input characteristics are extracted from the voice input and are then applied to the output voice segments to thereby provide a more realistic human sounding voice output.

US Patent:

6567962, May 20, 2003

Filed:

Nov 30, 2000

Appl. No.:

09/726289

Inventors:

Jason Raymond Baumgartner - Austin TX
Robert Neill Newshutz - Rochester MN
Steven Leonard Roberts - Austin TX
Anson Jeffrey Tripp - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6, 716 7, 716 11, 716 16, 716 18

Abstract:

An apparatus performs a process for partitioning a netlist. The process picks a unique color for each clock and traverses the clock tree coloring the latches in support of that clock tree with that color. The process then colors the fanout logic cones for each latch and notes any coloring collisions. In the case of a multicolored gate, the process retimes the network by moving the terminating latch backwards, towards the collision, to enable single coloring of the gate. The process then performs a depth-first search on the fanout logic of each primary input to the first latch encountered or a primary output. If a primary output is encountered, the path is colored with a color representing the free-run domain. Otherwise, the process colors the path with the color of the terminating latch. Next, the process duplicates the fanin cones for remaining multicolored gates so that a copy of the logic can be incorporated with each independent domain.

US Patent:

6553514, Apr 22, 2003

Filed:

Sep 23, 1999

Appl. No.:

09/404281

Inventors:

Jason Raymond Baumgartner - Austin TX
Nadeem Malik - Austin TX
Steven Leonard Roberts - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305

US Classification:

714 32, 714 33, 714724, 714741, 703 13, 703 14, 703 15, 703 16, 716 4, 716 5

Abstract:

A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state. In one embodiment useful for extending the verification coverage provided by a conventional non-formal verification technique, the non-formal tool is used to verify satisfaction of a specification or rule by traversing a first transition path of the circuit.

US Patent:

6564356, May 13, 2003

Filed:

Nov 2, 2000

Appl. No.:

09/704598

Inventors:

Nadeem Malik - Austin TX
Steven Leonard Roberts - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 4, 716 5

Abstract:

A coverage analysis process and apparatus assigns a unique label for every unique cycle of data produced by simulation or testing. The labels are substituted for the signal evaluations producing a graph of labels over time. The coverage analysis then generates a function, which represents the graph and the function is stored. The functions are analyzed and compared to determine coverage information. The coverage analysis process and apparatus provides significant data compression and represents the coverage in a form, which can easily be analyzed and compared.

US Patent:

6678417, Jan 13, 2004

Filed:

Nov 30, 1999

Appl. No.:

09/451951

Inventors:

Jason Raymond Baumgartner - Austin TX
Nadeem Malik - Austin TX
Steven Leonard Roberts - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K 936

US Classification:

382236, 382103, 348153

Abstract:

A method and system for transmitting video data are disclosed. The method includes receiving a first video image and comparing the first video image to at least one stock image where each of the stock images is associated with a corresponding index value. If a match between at least a portion of the first video image and one of the at least one stock images is detected, the index value corresponding to the matching stock image is transmitted over a transmission medium. In one embodiment, the method further includes receiving the transmitted index value and generating the corresponding stock image from the index value. The method of may further includes comparing the first video image with a set of stock images. If it is determined that the first image does not match to any of the set of stock images, then a new index value is assigned to the first image and the first image is added to the set of stock images. In one embodiment, the new index value and the corresponding video image are then transmitted to a receiving device.

US Patent:

6738955, May 18, 2004

Filed:

Nov 30, 2000

Appl. No.:

09/726283

Inventors:

Flemming Andersen - Austin TX
Jason Raymond Baumgartner - Austin TX
Steven Leonard Roberts - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 4, 703 16, 703 17, 703 21, 703 22, 703 28, 717104, 717126, 717128, 717135, 709201

Abstract:

A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.