Steven K Sherman

US Patent:

6985281, Jan 10, 2006

Filed:

Nov 27, 2002

Appl. No.:

10/306056

Inventors:

Matthias Wagner - Cambridge MA, US
Robert Murano - Malden MA, US
Eugene Y. Ma - Chestnut Hill MA, US
Steven Sherman - Boston MA, US
Lawrence H. Domash - Conway MA, US

Assignee:

Aegis Semiconductor, Inc. - Woburn MA

International Classification:

G02F 1/29

US Classification:

359315, 359578

Abstract:

An optoelectronic device including a header having an upper surface and including a plurality of conducting pins extending up through the upper surface; an optical device; a tunable optical filter, wherein the optical device and the tunable optical filter are arranged in a vertical stack mounted on and extending above the upper surface of the header and wherein the tunable optical filter is electrically connected to the plurality of conducting pins; and a cap affixed to the header and along with the header defining a sealed interior containing the optical device and the tunable optical filter, wherein the cap has a top surface with a window formed therein, and wherein the window is aligned with the tunable optical filter and the optical device.

US Patent:

8598891, Dec 3, 2013

Filed:

Feb 25, 2013

Appl. No.:

13/775335

Inventors:

William A. Clark - Winchester MA, US
John A. Geen - Tewksbury MA, US
Edward Wolfe - North Andover MA, US
Steven Sherman - Lexington MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G01R 27/28

US Classification:

324649, 32476201, 32475403, 32476205, 3592241, 438 14, 7351417

Abstract:

Detecting and/or mitigating the presence of particle contaminants in a MEMS device involves converting benign areas in which particles might become trapped undetectably by electric fields during test to field-free regions by extending otherwise non-functional conductive shield and gate layers and placing the same electrical potential on the conductive shield and gate layers. Particle contaminants can then be moved into detection locations remote from the potential trap areas and having particle detection structures by providing some mechanical disturbance.

US Patent:

20070184656, Aug 9, 2007

Filed:

Feb 6, 2007

Appl. No.:

11/671860

Inventors:

Steven Sherman - Newton MA, US
Arthur Learn - Cupertino CA, US
Robert Geffken - Burlington VT, US
John Hautala - Beverly MA, US

Assignee:

TEL EPION INC. - Billerica MA

International Classification:

H01L 21/44

US Classification:

438687000

Abstract:

A wafer processing cluster tool and method of operation provides one or more gas cluster ion beam processing chambers in possible combination with a deposition chamber and/or a cleaning chamber for performing sequential processing steps including, GCIB processing in a reduced pressure atmosphere.

US Patent:

20090233004, Sep 17, 2009

Filed:

Mar 17, 2008

Appl. No.:

12/049583

Inventors:

Steven Sherman - Newton MA, US
John J. Hautala - Beverly MA, US
Noel Russell - Waterford NY, US
Martin D. Tabat - Nashua NH, US
Thomas G. Tetreault - Manchester NH, US

Assignee:

TEL EPION INC. - Billerica MA

International Classification:

C23C 14/14

US Classification:

427527

Abstract:

A method for depositing material on a substrate is described. The method comprises maintaining a reduced-pressure environment around a substrate holder for holding a substrate having a surface, and holding the substrate securely within the reduced-pressure environment. Additionally, the method comprises forming a gas cluster ion beam (GCIB) from a pressurized gas comprising a compound having silicon (Si) and carbon (C), accelerating the GCIB to the reduced-pressure environment, and irradiating the accelerated GCIB onto at least a portion of the surface of the substrate to form a thin film containing silicon and carbon, wherein the carbon content is greater than or equal to about 10%. Further the compound may possess a Si—C bond.

US Patent:

20120164379, Jun 28, 2012

Filed:

Jan 27, 2011

Appl. No.:

13/015074

Inventors:

Steven Sherman - Newton MA, US
Leo van Glabbeek - Franklin MA, US
Weidong Huang - Bolton MA, US
Stephen Yamartino - Wayland MA, US
Kaitlin Olsen - Arlington MA, US

Assignee:

Evergreen Solar, Inc. - Marlborough MA

International Classification:

B32B 3/00
C30B 15/20
B32B 5/00

US Classification:

428141, 428220, 428172, 428174, 117 13

Abstract:

A sheet wafer has a generally flat, generally rectangular shaped body with a length and a width, and first and second filaments generally perpendicular to the width of the body. The first and second filaments are at least partially encapsulated by a wafer material and, together with the wafer material, form at least a portion of the body. The width is between about 145 mm and 165 mm.

US Patent:

20130167588, Jul 4, 2013

Filed:

Aug 9, 2012

Appl. No.:

13/570885

Inventors:

Steven Sherman - Newton MA, US
Leo van Glabbeek - Franklin MA, US
Stephen Yamartino - Wayland MA, US

International Classification:

H01L 21/02

US Classification:

65 325, 65193, 65157, 65172, 65203, 65 90

Abstract:

A sheet wafer furnace has a chamber having an opening, and a crucible, within the chamber, and spaced from the opening. The furnace also has a puller configured to pull a sheet wafer from molten material in the crucible and through the opening in the chamber, and a seal across the opening of the chamber.

US Patent:

20130285177, Oct 31, 2013

Filed:

Apr 29, 2013

Appl. No.:

13/872903

Inventors:

Steven Sherman - Newton MA, US
John J. Hautala - Beverly MA, US
Simon Ruffell - Beverly MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 43/02
H01L 43/12

US Classification:

257421, 438 3

Abstract:

In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.

US Patent:

20130288394, Oct 31, 2013

Filed:

Apr 29, 2013

Appl. No.:

13/872888

Inventors:

Steven Sherman - Newton MA, US
John J. Hautala - Beverly MA, US
Simon Ruffell - Beverly MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 43/12

US Classification:

438 3

Abstract:

A method of forming a magnetic memory includes providing a layer stack comprising a plurality of magnetic layers and a plurality of electrically conducting layers on a base portion of a substrate; forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, the first mask feature and second mask feature defining an exposed region of the layer stack in portions of the layer stack therebetween; and directing ions towards exposed the region of the layer stack in an ion exposure that is effective to magnetically isolate the first protected region from the second protected region and to electrically isolate the first protected region from the second protected region without removal of the exposed region of the layer stack.