Steven Craig Swanson

US Patent:

7490218, Feb 10, 2009

Filed:

Nov 22, 2005

Appl. No.:

11/284760

Inventors:

Susan Jane Eggers - Seattle WA, US
Martha Allen Mercaldi - Seattle WA, US
Kenneth Alan Michelson - New York NY, US
Mark Henry Oskin - Seattle WA, US
Andrew Kinoshita Petersen - Seattle WA, US
Andrew Richard Putnam - Seattle WA, US
Andrew Michalski Schwerin - Seattle WA, US
Steven James Swanson - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 15/00
G06F 15/76

US Classification:

712 25

Abstract:

A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar. ” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i. e. , a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks.

US Patent:

7657882, Feb 2, 2010

Filed:

Jan 21, 2005

Appl. No.:

11/041396

Inventors:

Mark H. Oskin - Seattle WA, US
Steven J. Swanson - Seattle WA, US
Susan J. Eggers - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 9/45

US Classification:

717156, 717149, 717155, 717161, 712 25, 712201

Abstract:

A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

US Patent:

8612955, Dec 17, 2013

Filed:

Jan 22, 2008

Appl. No.:

12/017480

Inventors:

Mark H. Oskin - Seattle WA, US
Steven J. Swanson - Seattle WA, US
Susan J. Eggers - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 9/45

US Classification:

717156, 717149, 717155, 717161, 712 25, 712201

Abstract:

A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

US Patent:

20030115415, Jun 19, 2003

Filed:

Dec 18, 2001

Appl. No.:

10/025266

Inventors:

Roy Want - Los Altos CA, US
James Kardach - Saratoga CA, US
Graham Kirby - San Jose CA, US
Trevor Pering - Mountain View CA, US
Steven Swanson - Seattle WA, US

International Classification:

G06F012/00
G06F012/14

US Classification:

711/115000

Abstract:

A method and device is provided for communicating with an access device. The device includes a wireless communications module to communicate with the access device in a wireless fashion, a data storage module to store bulk data, and a controller connected to the communication module and to the data storage module. The controller controls storage of data in the data storage module and retrieval of data from the data storage module in response to requests from a user via the access device. The device may function as a personal server which, for example, communicates with an access device (e.g., PC, PDA, cellular telephone, or the like) using Bluetooth technology. As Bluetooth is a universally accepted communication standard, a variety of different access devices, or any one particular preferred interface, in proximity to the user may be used to define a personal computing environment.

US Patent:

20060211022, Sep 21, 2006

Filed:

Feb 23, 2006

Appl. No.:

11/361415

Inventors:

Shuqian Jing - Palo Alto CA, US
Francesca Civoli - Newbury Park CA, US
Shalini Gupta - Newbury Park CA, US
Daniel Halperin - Calabasas CA, US
Jason Pennucci - Santa Monica CA, US
Steven Swanson - Moorpark CA, US
Yan Yu - Thousand Oaks CA, US

Assignee:

Amgen Inc. - Thousand Oaks CA

International Classification:

C12Q 1/68
G01N 33/53

US Classification:

435006000, 435007100

Abstract:

The present invention relates to methods of detecting compounds that affect the activity of a therapeutic substance or composition administered to a subject, and to reagents for use in such methods.

US Patent:

20070271556, Nov 22, 2007

Filed:

Jul 30, 2007

Appl. No.:

11/830446

Inventors:

Susan Eggers - Seattle WA, US
Martha Mercaldi - Seattle WA, US
Kenneth Michelson - New York NY, US
Mark Oskin - Seattle WA, US
Andrew Petersen - Seattle WA, US
Andrew Putnam - Seattle WA, US
Andrew Schwerin - Seattle WA, US
Steven Swanson - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 9/45

US Classification:

717151000

Abstract:

A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.