Steven W Weiss

US Patent:

6571360, May 27, 2003

Filed:

Oct 19, 1999

Appl. No.:

09/422204

Inventors:

Daniel P. Drogichen - Leucadia CA
Eric Eugene Graf - Hillsboro OR
Don Kane - San Diego CA
Douglas B. Meyer - San Diego CA
Andrew E. Phelps - Encinitas CA
Patricia Shanahan - San Diego CA
Steven F. Weiss - San Diego CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 44, 714 40

Abstract:

A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test.

US Patent:

6920584, Jul 19, 2005

Filed:

Nov 2, 2001

Appl. No.:

10/007625

Inventors:

Andrew E. Phelps - Encinitas CA, US
Steven F. Weiss - San Diego CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F011/00

US Classification:

714 32, 714 37

Abstract:

The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.

Address:

1370 Elderwood Dr, Corona, CA 92882

Phone:

(951)3332837

VIN:

5NPEB4AC2BH188817

Make:

HYUNDAI

Model:

SONATA

Year:

2011