Stuart T Albert

US Patent:

49655817, Oct 23, 1990

Filed:

Jan 8, 1990

Appl. No.:

7/461943

Inventors:

William J. Skudera - Oceanport NJ
Stuart D. Albert - Bricktown NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

G01S 736
H04B 110

US Classification:

342 19

Abstract:

A real-time rejection circuit for passing low level desired signals in the resence of one or more strong, interfering signals. A chirp-Z transform system separates the various frequency components of a received signal into frequency segregated time domain signals. A power splitter separates the time domain signal into two paths. One path includes a modulator or switch that is normally biased "ON" for passing the time domain signal. The second path includes a diode detector that produces pulses of sufficient strength when a strong interfering component is present to override the bias and turn the modulator "OFF" for a sufficient period of time to attenuate the unwanted frequency components in the other path. The modulator output will primarily contain the low level desired frequency components that are passed through an inverse transform device for producing a frequency domain signal of the desired signal uncorrupted by unwanted signals.

US Patent:

54246741, Jun 13, 1995

Filed:

Nov 18, 1992

Appl. No.:

7/977942

Inventors:

William J. Skudera - Oceanport NJ
Elio A. Mariani - Hamilton Square NJ
Stuart D. Albert - Bricktown NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H04B 110

US Classification:

327552

Abstract:

Two wide dynamic range detection circuits are disclosed, which are capable of detecting low-level desired signals in the presence of nearby strong interfering signals. Each circuit includes an attenuator scheme for attenuating the interfering signal while passing the desired signal. The first attenuator scheme uses a YIG filter in combination with an automatic gate arrangement. The second attenuator scheme uses a two-channel arrangement. The first channel uses a chirp-Z processor to derive a pulse-type transform signal in response to the strong interference signal. The second channel includes a YIG filter followed by a programmable notch filter which is controlled by the interference-signal pulse from the first channel. Following the programmable notch filter in the second channel is a chirp-Z processor followed by a gate arrangement wherein the gates are switched "OFF" under control of the interference-signal pulse from the first channel.