Subhasis Bose

US Patent:

7669160, Feb 23, 2010

Filed:

May 4, 2007

Appl. No.:

11/744758

Inventors:

Geoffrey Mark Furnish - Austin TX, US
Maurice J. LeBrun - Austin TX, US
Subhasis Bose - Austin TX, US

International Classification:

G06F 17/50

US Classification:

716 9, 716 10

Abstract:

Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. The forces are optionally selectively modulated as a function of simulation time. The placements of the devices are compatible with various design flows, such as standard cell, structured array, gate array, and field-programmable gate array.

US Patent:

7752588, Jul 6, 2010

Filed:

Dec 29, 2007

Appl. No.:

11/967180

Inventors:

Subhasis Bose - Austin TX, US

International Classification:

G06F 17/50

US Classification:

716 10, 716 6, 716 8, 716 9, 716 11

Abstract:

Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.

US Patent:

7814451, Oct 12, 2010

Filed:

Dec 29, 2007

Appl. No.:

11/967179

Inventors:

Geoffrey Mark Furnish - Austin TX, US
Maurice J. LeBrun - Austin TX, US
Subhasis Bose - Austin TX, US

International Classification:

G06F 17/50

US Classification:

716 6, 716 9, 716 10

Abstract:

Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations.

US Patent:

7921392, Apr 5, 2011

Filed:

Dec 29, 2007

Appl. No.:

11/967184

Inventors:

Geoffrey Mark Furnish - Austin TX, US
Maurice J. LeBrun - Austin TX, US
Subhasis Bose - Austin TX, US

Assignee:

Otrsotech, Limited Liability Company - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716110, 716119, 716122, 716126

Abstract:

Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations.

US Patent:

7921393, Apr 5, 2011

Filed:

Dec 29, 2007

Appl. No.:

11/967185

Inventors:

Geoffrey Mark Furnish - Austin TX, US
Maurice J. LeBrun - Austin TX, US
Subhasis Bose - Austin TX, US

Assignee:

Otrsotech, Limited Liability Company - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716110, 716119, 716122, 716126

Abstract:

Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node population.

US Patent:

8332793, Dec 11, 2012

Filed:

May 18, 2007

Appl. No.:

12/301456

Inventors:

Subhasis Bose - Austin TX, US

Assignee:

Otrsotech, LLC - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716114, 716108, 716113, 716119, 716122, 716134

Abstract:

Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.

US Patent:

20070150846, Jun 28, 2007

Filed:

Mar 9, 2007

Appl. No.:

11/684522

Inventors:

Geoffrey Furnish - Austin TX, US
Maurice LeBrun - Austin TX, US
Subhasis Bose - Austin TX, US

International Classification:

G06F 17/50
G06F 17/10

US Classification:

716008000, 703002000, 703004000

Abstract:

Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. The forces are optionally selectively modulated as a function of simulation time. The placements of the devices are compatible with various design flows, such as standard cell, structured array, gate array, and field-programmable gate array.