Suhas Anand Shetty

US Patent:

6633563, Oct 14, 2003

Filed:

Mar 2, 1999

Appl. No.:

09/260785

Inventors:

Arthur Lin - San Ramon CA
Kent Huntley Headrick - Newark CA
Suhas Anand Shetty - San Jose CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04L 1200

US Classification:

370389

Abstract:

A content addressable memory (CAM) having a search field, a mask and an output for each CAM location is used to efficiently determine a processor for processing IP packets, with each IP packet being received as a sequence of cells. IP packets may be assigned to a processor (group) based on an examination of the header data, potentially including IP header and other higher layer protocols headers. The search field of a CAM location is pre-stored with header data, and the bit positions to be searched in the location are specified by using a mask. The output of the location identifies the processor group for executing packets with headers matching the search field, with only the bits specified by the mask being compared. When a first cell of an IP packet is received, the header data is provided as an input to the CAM, and the output identifies the processor (group) for executing the IP packet.

US Patent:

6952728, Oct 4, 2005

Filed:

Dec 1, 1999

Appl. No.:

09/600054

Inventors:

Anthony L. Alles - Sunnyvale CA, US
Arthur Lin - San Ramon CA, US
Shyam Prasad Pillalamarri - Palo Alto CA, US
Kent H. Headrick - Milpitas CA, US
David A. Mullenex - Foster City CA, US
Suhas A. Shetty - San Jose CA, US

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

G06F015/173

US Classification:

709224, 709226

Abstract:

An internet service node (ISN) enabling the provision of desired service policies to each subscriber. The ISN may contain multiple processor groups, with each subscriber being assigned to a processor group. The assigned processor group may be configured with the processing rules, which provide the service policies desired, by a subscriber. A port may determine the specific processor group to which received data is to be forwarded. A content addressable memory with masks for individual locations may be implemented to quickly determines the processor group to which received data is to be assigned to. Due to the features of the present invention, an ISN may be able to serve a large number of subscribers efficiently. The ISN may be used at the edge of an access network.

US Patent:

7039764, May 2, 2006

Filed:

Jan 17, 2002

Appl. No.:

10/052718

Inventors:

Suhas Shetty - San Jose CA, US
De Vu - Fremont CA, US

Assignee:

Nokia Corporation - Espoo

International Classification:

G06F 12/00

US Classification:

711133

Abstract:

A method and a search engine are described. A unique key is received. A hash is searched for a match to the unique key. Concurrently with searching the hash, a cache is searched for the match to the unique key. And information regarding the unique key is obtained.

US Patent:

8059650, Nov 15, 2011

Filed:

Oct 31, 2007

Appl. No.:

11/932656

Inventors:

Suhas A. Shetty - San Jose CA, US
De B. Vu - Fremont CA, US

Assignee:

Aruba Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/28

US Classification:

370392

Abstract:

A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.

US Patent:

57271844, Mar 10, 1998

Filed:

Jun 27, 1994

Appl. No.:

8/266975

Inventors:

Bryan M. Richter - Fremont CA
Stephen A. Smith - Palo Alto CA
Daniel G. Bezzant - Pleasanton CA
Suhas Anand Shetty - Sunnyvale CA
Arunachalam Vaidyanathan - Fremont CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1310
G06F 501

US Classification:

395500

Abstract:

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format.

US Patent:

57940142, Aug 11, 1998

Filed:

Jun 10, 1997

Appl. No.:

8/872330

Inventors:

Suhas Anand Shetty - Sunnyvale CA
Daniel G. Bezzant - Pleasonton CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1300

US Classification:

395500

Abstract:

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Status detection logic circuitry is included within the socket controller for detecting changes in status of selected signals and notifying the system adapter of the changes in status.

US Patent:

62924923, Sep 18, 2001

Filed:

May 20, 1998

Appl. No.:

9/081969

Inventors:

Flavio Giovanni Bonomi - Palo Alto CA
Suhas Anand Shetty - San Jose CA
De Bao Vu - Fremont CA
William Stanley Evans - Menlo Park CA

Assignee:

CSI Zeitnet (A Cabletron Systems Company) - Santa Clara CA

International Classification:

H04L 1254

US Classification:

370415

Abstract:

A switch guaranteeing a minimum amount of memory space for desired connection while allowing efficient dynamic change of maximum memory space that can be used by a connection. Only an amount of memory space which is required for guaranteeing the minimum amount of memory space is reserved. When the reserved space is decremented due to new cells being received on connections, the maximum memory space reserved for each connection is dynamically increased. For multicast connections, only a single copy of the cell data is stored even though a multicast cell is transmitted on several ports. Multicast cells can also be processed using the same signals used for processing unicast cells.

US Patent:

59058854, May 18, 1999

Filed:

Sep 19, 1997

Appl. No.:

8/933884

Inventors:

Bryan M. Richter - Fremont CA
Stephen A. Smith - Palo Alto CA
Daniel G. Bezzant - Pleasanton CA
Suhas Anand Shetty - Sunnyvale CA
Arunachalam Vaidyanathan - Fremont CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F13/10;5/01

US Classification:

395500

Abstract:

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format.