Suketu Arun Parikh

US Patent:

6391771, May 21, 2002

Filed:

Jul 23, 1998

Appl. No.:

09/121236

Inventors:

Mehul B. Naik - San Jose CA
Suketu A. Parikh - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438653, 438652, 438654, 438687, 438669, 438671, 438672, 438674, 438675, 438696, 438622, 257751, 257762

Abstract:

The present invention provides Cu lines which are enclosed within Cu diffusion barrier layers, for IC structures such as semiconductor devices. The Cu lines ( ) have conventional top ( ) and bottom ( ) Cu diffusion barrier layers and novel sidewall layers ( and ) comprising Cu diffusion barrier materials. The present invention also provides for conductive interconnect lines for semiconductor devices which compensate partly or completely for a misalignment between the line etch pattern and the underlying contact element, such as a via plug. The misalignment tolerant line ( ) is formed by fabricating novel sidewalls ( and ) on the line wherein the sidewalls have a thickness which equals or exceeds the width of the gap ( ) which is caused by the misalignment. The misalignment tolerant line compensates for the misalignment gap and thereby prevents etching a trench in the contact element. Trench formation is reduced rather than prevented when the sidewall is thinner than the width of the misalignment gap.

US Patent:

6514671, Feb 4, 2003

Filed:

Sep 29, 2000

Appl. No.:

09/675989

Inventors:

Suketu A. Parikh - Santa Clara CA
Mehul B. Naik - San Jose CA
Samuel Broydo - Los Altos Hills CA
H. Peter W. Hey - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G03C 500

US Classification:

430313, 430317, 438629, 438637, 438638, 216 16

Abstract:

The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures ( and ) are formed in consecutive dielectric layers ( and ) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask ( ) upon exposure to radiation. In additional embodiments, manufacturing systems ( ) are provided for fabricating IC structures. These systems include a controller ( ) which is adapted for interacting with a plurality of fabrication stations ( and ).

US Patent:

6594540, Jul 15, 2003

Filed:

Sep 29, 2000

Appl. No.:

09/675906

Inventors:

Suketu A. Parikh - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700121, 700119, 438618

Abstract:

The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers ( and ) having similar etching characteristics. Additionally, a hard mask layer ( ) and an etch stop layer ( ) having similar etching characteristics are used in these structures. In additional embodiments, manufacturing systems ( ) are provided for fabricating IC structures. These systems include a controller ( ) for interacting with a plurality of fabrication stations ( and ).

US Patent:

6656840, Dec 2, 2003

Filed:

Apr 29, 2002

Appl. No.:

10/136455

Inventors:

Nagarajan Rajagopalan - Santa Clara CA
Joe Feng - Cupertino CA
Christopher S Ngai - Burlingame CA
Suketu A Parikh - San Jose CA
Linh H Thanh - Cupertino CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438687, 438622, 438680, 438791, 438792

Abstract:

A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.

US Patent:

6842659, Jan 11, 2005

Filed:

Aug 24, 2001

Appl. No.:

09/939073

Inventors:

Suketu Parikh - San Jose CA, US
Robin Cheung - Cupertino CA, US

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700121

Abstract:

A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

US Patent:

6940170, Sep 6, 2005

Filed:

Apr 26, 2001

Appl. No.:

09/843419

Inventors:

Suketu A. Parikh - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L029/00
H01L021/44
H01L023/485

US Classification:

257750, 257751, 257752, 257758, 257775, 438600, 438622, 438637, 438638, 438700, 438738, 438740

Abstract:

The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (and ), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (), on the fifth (top) layer (), developing a power line trench pattern () and a via pattern () in the first mask layer, simultaneously etching the power line trench pattern () and the via pattern () through the top three dielectric layers (), and removing the first etch mask layer. A second etching sequence including: depositing a second etch mask layer (), on the fifth layer () and inside the power line trench () formed in the first etching sequence, developing a signal line pattern () overlaying the via pattern () in the second etch layer, etching the via pattern () through the second layer (), and subsequently etching the via pattern () through the first layer() while simultaneously etching the signal line trench pattern () through the fifth layer (). The etching sequences result in the formation of a power line trench () and a signal line trench () with an underlying via hole (). These trenches and the via hole are simultaneously filled with a conductive material, such as a metal, to form a triple damascene structure including a power line () and a signal line () having an underlying via plug ().

US Patent:

7074626, Jul 11, 2006

Filed:

Mar 19, 2004

Appl. No.:

10/804324

Inventors:

Suketu Parikh - San Jose CA, US
Robin Cheung - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00
H01L 21/66

US Classification:

438 5, 438 14

Abstract:

A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

US Patent:

7205228, Apr 17, 2007

Filed:

Mar 30, 2004

Appl. No.:

10/812480

Inventors:

Deenesh Padhi - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Mehul Naik - San Jose CA, US
Suketu A. Parikh - San Jose CA, US
Girish A. Dixit - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438652, 438670, 438678

Abstract:

A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.