Sung W Jo

US Patent:

8274812, Sep 25, 2012

Filed:

Jun 14, 2010

Appl. No.:

12/815369

Inventors:

Hagop Nazarian - San Jose CA, US
Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365148, 365149, 36518909

Abstract:

A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

US Patent:

8391049, Mar 5, 2013

Filed:

Sep 29, 2010

Appl. No.:

12/894087

Inventors:

Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365148, 365 63, 36518519

Abstract:

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

US Patent:

8411485, Apr 2, 2013

Filed:

Jun 14, 2010

Appl. No.:

12/815318

Inventors:

Hagop Nazarian - San Jose CA, US
Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365148, 36518501, 365 46, 365149, 365150, 365163

Abstract:

A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

US Patent:

8426306, Apr 23, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/341835

Inventors:

Harry Gee - Sunnyvale CA, US
Sung Hyun Jo - Sunnyvale CA, US
Hagop Nazarian - San Jose CA, US
Scott Brad Herner - San Jose CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

H01L 21/4763

US Classification:

438622, 438624, 438637, 438239, 257 2, 257 4, 257 5

Abstract:

A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.

US Patent:

8441835, May 14, 2013

Filed:

Jun 11, 2010

Appl. No.:

12/814410

Inventors:

Sung Hyun Jo - Sunnyvale CA, US
Hagop Nazarian - San Jose CA, US
Wei Lu - Ann Arbor MI, US

Assignee:

Crossbar, Inc. - Menlo Park CA

International Classification:

G11C 11/00

US Classification:

365148, 365158

Abstract:

A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

US Patent:

8467227, Jun 18, 2013

Filed:

Nov 4, 2011

Appl. No.:

13/290024

Inventors:

Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365148, 365158, 365 51, 365171

Abstract:

A non-volatile memory device includes a first electrode, a resistive switching material stack overlying the first electrode. The resistive switching material stack comprising a first resistive switching material and a second resistive switching material. The second resistive switching material overlies the first electrode and the first resistive switching material overlying the second resistive switching material. The first resistive switching material is characterized by a first switching voltage having a first amplitude. The second resistive switching material is characterized by a second switching voltage having a second amplitude no greater than the first switching voltage. A second electrode comprising at least a metal material physically and electrically in contact with the first resistive switching material overlies the first resistive switching material.

US Patent:

8558212, Oct 15, 2013

Filed:

Sep 29, 2010

Appl. No.:

12/894098

Inventors:

Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

H01L 45/00
H01L 21/02

US Classification:

257 4, 257E21085, 257E45005, 438382

Abstract:

A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

US Patent:

8569172, Oct 29, 2013

Filed:

Aug 14, 2012

Appl. No.:

13/585759

Inventors:

Sung Hyun Jo - Sunnyvale CA, US
Tanmay Kumar - Pleasanton CA, US

Assignee:

Crossbar, Inc. - Santa Clara

International Classification:

H01L 21/44
H01L 21/00

US Classification:

438686, 438381, 438685, 257261, 257608, 257E27004, 257E25014, 365148, 365174

Abstract:

A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.