Sung Mo Jun

US Patent:

20090149008, Jun 11, 2009

Filed:

Oct 2, 2008

Appl. No.:

12/244440

Inventors:

Olga Kryliouk - Santa Clara CA, US
Sandeep Nijhawan - Los Altos CA, US
Yuriy Melnik - Santa Clara CA, US
Lori D. Washington - Union City CA, US
Jacob W. Grayson - Santa Clara CA, US
Sung W. Jun - Sunnyvale CA, US
Jie Su - Santa Clara CA, US

International Classification:

H01L 21/20

US Classification:

438503, 257E2109

Abstract:

Embodiments of the invention generally relate to methods for forming Group III-V materials by a hydride vapor phase epitaxy (HVPE) process. In one embodiment, a method for forming a gallium nitride material on a substrate within a processing chamber is provided which includes heating a metallic source to form a heated metallic source, wherein the heated metallic source contains gallium, aluminum, indium, alloys thereof, or combinations thereof, exposing the heated metallic source to chlorine gas while forming a metallic chloride gas, exposing the substrate to the metallic chloride gas and a nitrogen precursor gas while forming a metal nitride layer on the substrate during the HVPE process. The method further provides exposing the substrate to chlorine gas during a pretreatment process prior to forming the metal nitride layer. In one example, the exhaust conduit of the processing chamber is heated to about 200 C. or less during the pretreatment process.

US Patent:

20100273291, Oct 28, 2010

Filed:

Mar 24, 2010

Appl. No.:

12/731030

Inventors:

Olga Kryliouk - Sunnyvale CA, US
Jie Su - Santa Clara CA, US
Kevin Griffin - Livermore CA, US
Sung Won Jun - Cupertino CA, US
Xizi Dong - Santa Clara CA, US
Tze Poon - Sunnyvale CA, US
Lori D. Washington - Union City CA, US
Jacob Grayson - Midland MI, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

H01L 51/40

US Classification:

438 99, 118715, 257E51001

Abstract:

Embodiments of the present invention generally relate to methods and apparatus for removing unwanted deposition build-up from one more interior surfaces of a substrate processing chamber after a substrate is processed in a chamber to form, for example, Group III-V materials by metal-organic chemical vapor deposition (MOCVD) deposition processes and/or hydride vapor phase epitaxial (HVPE) deposition processes. In one embodiment, a method for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber is provided. The method comprises depositing one or more Group III containing layers over a substrate disposed in the substrate processing chamber, transferring the substrate out of the substrate processing chamber, and pulsing a halogen containing gas into the substrate processing chamber to remove at least a portion of the unwanted deposition build-up from one or more interior surfaces of the substrate processing chamber.

US Patent:

20110104843, May 5, 2011

Filed:

Jul 23, 2010

Appl. No.:

12/842908

Inventors:

Sung Won Jun - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 33/06

US Classification:

438 45, 438 47, 257E3301, 257E33034

Abstract:

A method of fabricating a light emitting diode. According to embodiments of the present invention an active region comprising a plurality of gallium nitride (GaN) barrier layers and a plurality of indium gallium nitride (InGan) quantum well layers are formed over a substrate. A p-type gallium nitride layer is formed above the active region by a hydride vapor phase epitaxy (HVPE) at a high deposition rate.

US Patent:

20130005118, Jan 3, 2013

Filed:

Jun 28, 2012

Appl. No.:

13/535845

Inventors:

Sung Won Jun - Cupertino CA, US
Yan Wang - Sunnyvale CA, US
Hua Chung - San Jose CA, US
Jiang Lu - Milpitas CA, US
Kuan Chien Keris Shen - Santa Clara CA, US
Shiva Rai - Champaign IL, US

International Classification:

H01L 21/205

US Classification:

438478, 257E21112

Abstract:

Methods of forming III-V materials using metal organic chemical vapor deposition (MOCVD) with chlorine cleans operations are described. A chlorine-clean operation may further season an MOCVD process for improved throughput for high volume manufacturing.

US Patent:

20200035822, Jan 30, 2020

Filed:

Oct 3, 2019

Appl. No.:

16/592362

Inventors:

- Santa Clara CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Theresa Kramer GUARINI - San Jose CA, US
Sung Won JUN - San Jose CA, US
Vanessa PENA - Heverlee, BE
Errol Antonio C. SANCHEZ - Tracy CA, US
Benjamin COLOMBEAU - Salem MA, US
Michael CHUDZIK - Mountain View CA, US
Bingxi WOOD - Cupertino CA, US
Nam Sung KIM - Sunnyvale CA, US

International Classification:

H01L 29/78
H01L 29/423
H01L 29/786
H01L 29/10

Abstract:

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

US Patent:

20180061978, Mar 1, 2018

Filed:

Nov 6, 2017

Appl. No.:

15/804691

Inventors:

- Santa Clara CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Theresa Kramer GUARINI - San Jose CA, US
Sung Won JUN - San Jose CA, US
Vanessa PENA - Heverlee, BE
Errol Antonio C. SANCHEZ - Tracy CA, US
Benjamin COLOMBEAU - Salem MA, US
Michael CHUDZIK - Mountain View CA, US
Bingxi Sun WOOD - Cupertino CA, US
Nam Sung KIM - Sunnyvale CA, US

International Classification:

H01L 29/78
H01L 29/10
H01L 29/786
H01L 29/423

Abstract:

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

US Patent:

20170018624, Jan 19, 2017

Filed:

Sep 28, 2016

Appl. No.:

15/279257

Inventors:

- Santa Clara CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Theresa Kramer GUARINI - San Jose CA, US
Sung Won JUN - San Jose CA, US
Benjamin COLOMBEAU - Salem MA, US
Michael CHUDZIK - Mountain View CA, US

International Classification:

H01L 29/423
H01L 21/306
H01L 21/762
H01L 21/02

Abstract:

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

US Patent:

20160336405, Nov 17, 2016

Filed:

May 11, 2016

Appl. No.:

15/152273

Inventors:

- Santa Clara CA, US
Naomi YOSHIDA - Sunnyvale CA, US
Theresa Kramer GUARINI - San Jose CA, US
Sung Won JUN - San Jose CA, US
Vanessa PENA - Heverlee, BE
Errol Antonio C. SANCHEZ - Tracy CA, US
Benjamin COLOMBEAU - Salem MA, US
Michael CHUDZIK - Mountain View CA, US
Bingxi WOOD - Cupertino CA, US
Nam Sung KIM - Sunnyvale CA, US

International Classification:

H01L 29/15
H01L 29/423
H01L 29/06
H01L 29/49
H01L 29/45
H01L 29/165
H01L 29/78

Abstract:

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.