Suresh H Parameswaran

US Patent:

7403446, Jul 22, 2008

Filed:

Sep 27, 2005

Appl. No.:

11/237378

Inventors:

Suresh Parameswaran - Fremont CA, US
Thinh Tran - Palo Alto CA, US
Joseph Tzou - Mountain View CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 7/00
G11C 8/00

US Classification:

3652331, 36518902, 36518905, 36518912, 36523008

Abstract:

Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.

US Patent:

7535772, May 19, 2009

Filed:

Jun 25, 2004

Appl. No.:

10/877932

Inventors:

Suresh Parameswaran - Milpitas CA, US
Thinh Tran - Palo Alto CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 7/00

US Classification:

36518902, 36523313, 36523318, 36523319, 365239, 36518905, 36518912, 36523002

Abstract:

Data paths ( and ) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path () can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path () can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path () can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180.

US Patent:

7719908, May 18, 2010

Filed:

Dec 21, 2007

Appl. No.:

11/963446

Inventors:

Joseph Tzou - Mountain View CA, US
Suresh Parameswaran - Fremont CA, US
Thinh Tran - Palo Alto CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 29/00

US Classification:

365201, 36518907, 36518904, 36518507

Abstract:

Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e. g. , an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory.

US Patent:

7728619, Jun 1, 2010

Filed:

Mar 31, 2008

Appl. No.:

12/059953

Inventors:

Joseph Jengtao Tzou - Mountain View CA, US
Suresh Parameswaran - Fremont CA, US
Thinh Dinh Tran - Palo Alto CA, US

International Classification:

H03K 17/16

US Classification:

326 30, 326 32, 36518511, 36518911

Abstract:

An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-overlapping manner. The circuit includes a plurality of chips arranged in a cascading configuration. A cascade output pin of a chip is coupled to a cascade input pin of a cascaded chip to enable handshaking between the plurality of chips. The plurality of chips are coupled to a common precision resistor via a common impedance line to enable each chip to calibrate impedance of the chip. Each of the plurality of chips includes a control circuit. Each control circuit includes a state machine circuit. The control circuit is configured to control a non-overlapping clock cycle of each chip during which the impedance of the chip is evaluated.

US Patent:

8040164, Oct 18, 2011

Filed:

Sep 29, 2008

Appl. No.:

12/286321

Inventors:

Suresh Parameswaran - Fremont CA, US
Joseph Tzou - Mountain View CA, US
Morgan Whately - San Francisco CA, US
Thinh Tran - Palo Alto CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03B 1/00
H03K 3/00

US Classification:

327109, 327108, 327110, 327111, 327112, 326 30, 326 82, 326 83

Abstract:

An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

US Patent:

7142477, Nov 28, 2006

Filed:

Jun 18, 2004

Appl. No.:

10/871825

Inventors:

Thinh Tran - Palo Alto CA, US
Joseph Tzou - Mountain View CA, US
Suresh Parameswaran - Milpitas CA, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523002, 36523008, 36523001

Abstract:

A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.

US Patent:

20140091819, Apr 3, 2014

Filed:

Sep 28, 2012

Appl. No.:

13/630215

Inventors:

- San Jose CA, US
Henley Liu - San Jose CA, US
Myongseob Kim - Pleasanton CA, US
Suresh P. Parameswaran - Fremont CA, US
Cheang-Whang Chang - Mountain View CA, US
Boon Y. Ang - Sunnyvale CA, US

Assignee:

XILINX, INC. - San Jose CA

International Classification:

G01R 31/3187

US Classification:

3247503

Abstract:

An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Address:

3100 Country Lk Ct, Austin, TX 78732

VIN:

JHMFA36208S027795

Make:

HONDA

Model:

CIVIC

Year:

2008