Surya Kiran Musunuri

US Patent:

20100073035, Mar 25, 2010

Filed:

Sep 25, 2008

Appl. No.:

12/238189

Inventors:

Praveen Dani - San Jose CA, US
Robert Fulton - Rancho Cordova CA, US
Andrew M. Volk - Granite Bay CA, US
Surya Musunuri - Roseville CA, US

International Classification:

H03B 21/00

US Classification:

327105

Abstract:

An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

US Patent:

20190173276, Jun 6, 2019

Filed:

Jan 28, 2019

Appl. No.:

16/259983

Inventors:

- Cupertino CA, US
Nagendra Bage Jayaraj - San Jose CA, US
Derek J. DiCarlo - San Jose CA, US
Chi Kin Ho - Milpitas CA, US
Xingqun Li - San Jose CA, US
Jahan C. Minoo - San Jose CA, US
Surya Musunuri - San Jose CA, US
Tony Chi Wang Ng - Santa Clara CA, US
Carlos Ribas - Los Altos CA, US
Ching Yu John Tam - Los Gatos CA, US
Evan J. Thompson - Sunnyvale CA, US
Daniel C. Wagman - Scotts Valley CA, US
Di Zhao - Santa Clara CA, US
Robert D. Zupke - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H02H 9/04
H01R 24/60
H04L 12/40
H01R 13/66
G06F 13/40
H01R 13/713

Abstract:

A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.

US Patent:

20170358922, Dec 14, 2017

Filed:

Sep 2, 2016

Appl. No.:

15/256409

Inventors:

- Cupertino CA, US
Nagendra Bage Jayaraj - San Jose CA, US
Derek J. DiCarlo - San Jose CA, US
Chi Kin Ho - Milpitas CA, US
Xingqun Li - San Jose CA, US
Jahan C. Minoo - San Jose CA, US
Surya Musunuri - San Jose CA, US
Tony Chi Wang Ng - Santa Clara CA, US
Carlos Ribas - Los Altos CA, US
Ching Yu John Tam - Los Gatos CA, US
Evan J. Thompson - Sunnyvale CA, US
Daniel C. Wagman - Scotts Valley CA, US
Di Zhao - Santa Clara CA, US
Robert D. Zupke - San Jose CA, US

International Classification:

H02H 9/04
H01R 24/60
H01R 13/66
H01R 13/713
H01R 107/00

Abstract:

A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.

US Patent:

20160204787, Jul 14, 2016

Filed:

Sep 26, 2013

Appl. No.:

14/127963

Inventors:

- Santa Clara CA, US
Mohamed A. ABDELSALAM - Giza, EG
Mamdouh O. ABD EL-MEJEED - Alexandria, EG
Nasser A. KURD - Portland OR, US
Mark ELZINGA - El Dorado CA, US
Young Min PARK - Folsom CA, US
Jagannadha R. RAPETA - Folsom CA, US
Surya MUSUNURI - Folsom CA, US

International Classification:

H03L 7/10
G04F 10/00
H03L 7/099

Abstract:

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.