Susan B Curtis

US Patent:

7064593, Jun 20, 2006

Filed:

Dec 14, 2004

Appl. No.:

11/012448

Inventors:

Gene B. Hinterscher - Mckinney TX, US
Susan A. Curtis - Sherman TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/02

US Classification:

327198, 327199, 327332

Abstract:

A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘I’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

US Patent:

8581629, Nov 12, 2013

Filed:

May 17, 2012

Appl. No.:

13/473715

Inventors:

Gary F. Chard - Garland TX, US
Scott A. Morrison - Richardson TX, US
Susan A. Curtis - Sherman TX, US
Daniel A. King - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/0175

US Classification:

326 82, 326 93, 326 95, 326 26, 327415

Abstract:

An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

US Patent:

20160035287, Feb 4, 2016

Filed:

Jul 29, 2015

Appl. No.:

14/812463

Inventors:

- Dallas TX, US
Harish Venkataraman - Wylie TX, US
Susan Curtis - Sherman TX, US

International Classification:

G09G 3/34
G09G 3/36

Abstract:

A display panel includes multiple pixel elements for composing an image and a control circuit for accessing each pixel element. The control circuit includes a data line for conducting a luminance signal and a selection line for conducting a selection signal. Each pixel element includes a switch, a display cell, and a compensatory capacitor. The switch is connected to the data line and the selection line, such that the switch can selectively deliver the luminance signal to the display cell. The display cell is configured to adjust its light transmittance in response to the received luminance signal. Being connected to the switch and the display cell, the compensatory capacitor is configured to receive a compensation signal corresponding to a transition of the selection signal and for correcting a parasitic effect at the display cell.

US Patent:

20150365087, Dec 17, 2015

Filed:

Jun 16, 2015

Appl. No.:

14/741208

Inventors:

- Dallas TX, US
Susan Ann CURTIS - Allen TX, US
David John BALDWIN - Allen TX, US

International Classification:

H03K 17/687
H02M 3/07

Abstract:

A switch includes a power transistor configured to switch an input voltage to a load. The switch further includes a charge pump and a duty cycle controller. The charge pump is coupled to the power transistor and includes an enable input to cause the charge pump to be turned on and off. The duty cycle controller is coupled to the charge pump and is configured to duty cycle the charge pump based on a comparison of a signal of a gate of the power transistor to a reference signal.

US Patent:

20150256136, Sep 10, 2015

Filed:

Mar 9, 2015

Appl. No.:

14/642602

Inventors:

- Dallas TX, US
Susan Ann Curtis - Allen TX, US
Harish Venkataraman - Wylie TX, US

International Classification:

H03F 3/04
G06F 3/044
G06F 3/047
G09G 5/00
H03F 1/02
G01D 5/24

Abstract:

A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, R, and feedback capacitor, C, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R and R and wherein the other side of the feedback capacitor is coupled between R and the output of the first amplifier, R is connected to Vfrom one side and Rand R from the other, R is connected to Rand R from one side and Cand output of the first amplifier from the other side, another resistor, R is connect to the output of the first amplifier, Cand R from one side and R yet another resistor, and input of amp from the other, a second amplifier, Amp is connected to the R and R at one input and 1.5v at the other input, and wherein the output of the second amplifier is connected to R and R connects to one input of the second amplifier and the output of the second amplifier.

US Patent:

20150130434, May 14, 2015

Filed:

Jul 30, 2014

Appl. No.:

14/446563

Inventors:

- Dallas TX, US
Timothy Bryan Merkin - Richardson TX, US
Susan Curtis - Allen TX, US

International Classification:

G05F 1/575

US Classification:

323280

Abstract:

A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.

US Patent:

20150130755, May 14, 2015

Filed:

Nov 3, 2014

Appl. No.:

14/531408

Inventors:

- Dallas TX, US
Harish Venkataraman - Wylie TX, US
Susan Curtis - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 3/044

US Classification:

345174

Abstract:

An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.